Hi,
coreboot-scanbuild.diff eliminates various issues brought up by scan-build.
coreboot-loglevel.diff adds an "-l <num>" argument to abuild that sets
the LOGLEVEL variables to the specified value.
coreboot-psd.diff adds a helper function to acpigen to create _PSD tables.
All of them are
Signed-off-by: Patrick Georgi <[email protected]>
Regards,
Patrick
Index: src/devices/pci_rom.c
===================================================================
--- src/devices/pci_rom.c (.../branches/upstream/coreboot-v2)
+++ src/devices/pci_rom.c (.../trunk/coreboot-v2)
@@ -42,7 +42,7 @@
printk_debug("In cbfs, rom address for %s = %lx\n",
dev_path(dev), rom_address);
if (v) {
- dev->rom_address = v;
+ dev->rom_address = (u32)v;
dev->on_mainboard = 1;
}
}
Index: src/devices/pci_device.c
===================================================================
--- src/devices/pci_device.c (.../branches/upstream/coreboot-v2)
+++ src/devices/pci_device.c (.../trunk/coreboot-v2)
@@ -10,7 +10,7 @@
* Copyright (C) 2004-2005 Li-Ta Lo <[email protected]>
* Copyright (C) 2005-2006 Tyan
* (Written by Yinghai Lu <[email protected]> for Tyan)
- * Copyright (C) 2005-2007 Stefan Reinauer <[email protected]>
+ * Copyright (C) 2005-2009 coresystems GmbH
*/
/*
@@ -271,7 +271,7 @@
{
struct resource *resource;
unsigned long value;
- resource_t moving, limit;
+ resource_t moving;
if ((dev->on_mainboard) && (dev->rom_address == 0)) {
//skip it if rom_address is not set in MB Config.lb
@@ -296,8 +296,6 @@
* - Limit is all of the bits that move plus all of the lower bits.
* See PCI Spec 6.2.5.1 ...
*/
- limit = 0;
-
if (moving) {
resource->size = 1;
resource->align = resource->gran = 0;
@@ -306,7 +304,7 @@
resource->align += 1;
resource->gran += 1;
}
- resource->limit = limit = moving | (resource->size - 1);
+ resource->limit = moving | (resource->size - 1);
}
if (moving == 0) {
@@ -927,7 +925,7 @@
if ( (id == 0xffffffff) || (id == 0x00000000) ||
(id == 0x0000ffff) || (id == 0xffff0000))
{
- printk_spew("%s, bad id 0x%x\n", dev_path(&dummy), id);
+ // printk_spew("PCI: devfn 0x%x, bad id 0x%x\n", devfn,
id);
return NULL;
}
dev = alloc_dev(bus, &dummy.path);
Index: src/include/console/console.h
===================================================================
--- src/include/console/console.h (.../branches/upstream/coreboot-v2)
+++ src/include/console/console.h (.../trunk/coreboot-v2)
@@ -10,7 +10,7 @@
unsigned char console_rx_byte(void);
int console_tst_byte(void);
void post_code(uint8_t value);
-void die(const char *msg);
+void __attribute__ ((noreturn)) die(const char *msg);
struct console_driver {
void (*init)(void);
Index: src/console/usbdebug_direct_console.c
===================================================================
--- src/console/usbdebug_direct_console.c
(.../branches/upstream/coreboot-v2)
+++ src/console/usbdebug_direct_console.c (.../trunk/coreboot-v2)
@@ -1,3 +1,4 @@
+#include <string.h>
#include <console/console.h>
#include <usbdebug_direct.h>
#include <pc80/mc146818rtc.h>
Index: src/boot/elfboot.c
===================================================================
--- src/boot/elfboot.c (.../branches/upstream/coreboot-v2)
+++ src/boot/elfboot.c (.../trunk/coreboot-v2)
@@ -362,9 +362,6 @@
seg->phdr_next->phdr_prev = new;
seg->phdr_next = new;
- /* compute the new value of end */
- end = start + len;
-
printk_spew(" late: [0x%016lx, 0x%016lx, 0x%016lx)\n",
new->s_addr,
new->s_addr + new->s_filesz,
Index: src/arch/i386/boot/coreboot_table.c
===================================================================
--- src/arch/i386/boot/coreboot_table.c (.../branches/upstream/coreboot-v2)
+++ src/arch/i386/boot/coreboot_table.c (.../trunk/coreboot-v2)
@@ -93,9 +93,8 @@
void add_console(struct lb_header *header, u16 consoletype)
{
- struct lb_record *rec;
struct lb_console *console;
- rec = lb_new_record(header);
+
console = (struct lb_console *)lb_new_record(header);
console->tag = LB_TAG_CONSOLE;
console->size = sizeof(*console);
Index: util/nrv2b/nrv2b.c
===================================================================
--- util/nrv2b/nrv2b.c (.../branches/upstream/coreboot-v2)
+++ util/nrv2b/nrv2b.c (.../trunk/coreboot-v2)
@@ -65,7 +65,7 @@
#define BITSIZE 32
#endif
-static __inline__ void Error(char *message)
+static __inline__ __attribute__((noreturn)) void Error(char *message)
{
Fprintf((stderr, "\n%s\n", message));
exit(EXIT_FAILURE);
Index: util/buildrom/buildrom.c
===================================================================
--- util/buildrom/buildrom.c (.../branches/upstream/coreboot-v2)
+++ util/buildrom/buildrom.c (.../trunk/coreboot-v2)
@@ -24,7 +24,7 @@
exit(1);
}
-void fatal(char *s)
+void __attribute__((noreturn)) fatal(char *s)
{
perror(s);
exit(2);
Index: targets/iwill/dk8_htx/Config-abuild.lb
===================================================================
--- targets/iwill/dk8_htx/Config-abuild.lb
(.../branches/upstream/coreboot-v2)
+++ targets/iwill/dk8_htx/Config-abuild.lb (.../trunk/coreboot-v2)
@@ -8,6 +8,7 @@
option HOSTCC="CROSS_HOSTCC"
__COMPRESSION__
+__LOGLEVEL__
romimage "normal"
option USE_FAILOVER_IMAGE=0
Index: targets/bcom/winnetp680/Config-abuild.lb
===================================================================
--- targets/bcom/winnetp680/Config-abuild.lb
(.../branches/upstream/coreboot-v2)
+++ targets/bcom/winnetp680/Config-abuild.lb (.../trunk/coreboot-v2)
@@ -8,6 +8,7 @@
option HOSTCC="CROSS_HOSTCC"
__COMPRESSION__
+__LOGLEVEL__
option ROM_SIZE=512*1024
Index: targets/thomson/ip1000/Config-abuild.lb
===================================================================
--- targets/thomson/ip1000/Config-abuild.lb
(.../branches/upstream/coreboot-v2)
+++ targets/thomson/ip1000/Config-abuild.lb (.../trunk/coreboot-v2)
@@ -26,6 +26,7 @@
option HOSTCC="CROSS_HOSTCC"
__COMPRESSION__
+__LOGLEVEL__
romimage "fallback"
option USE_FALLBACK_IMAGE = 1
Index: targets/supermicro/h8dmr/Config-abuild.lb
===================================================================
--- targets/supermicro/h8dmr/Config-abuild.lb
(.../branches/upstream/coreboot-v2)
+++ targets/supermicro/h8dmr/Config-abuild.lb (.../trunk/coreboot-v2)
@@ -8,6 +8,7 @@
option HOSTCC="CROSS_HOSTCC"
__COMPRESSION__
+__LOGLEVEL__
romimage "normal"
option USE_FAILOVER_IMAGE=0
Index: targets/supermicro/h8dme/Config-abuild.lb
===================================================================
--- targets/supermicro/h8dme/Config-abuild.lb
(.../branches/upstream/coreboot-v2)
+++ targets/supermicro/h8dme/Config-abuild.lb (.../trunk/coreboot-v2)
@@ -8,6 +8,7 @@
option HOSTCC="CROSS_HOSTCC"
__COMPRESSION__
+__LOGLEVEL__
romimage "normal"
option USE_FAILOVER_IMAGE=0
Index: targets/kontron/986lcd-m/Config-abuild.lb
===================================================================
--- targets/kontron/986lcd-m/Config-abuild.lb
(.../branches/upstream/coreboot-v2)
+++ targets/kontron/986lcd-m/Config-abuild.lb (.../trunk/coreboot-v2)
@@ -8,20 +8,21 @@
option HOSTCC="CROSS_HOSTCC"
__COMPRESSION__
+__LOGLEVEL__
option ROM_SIZE=1024*(1024-64)
option FALLBACK_SIZE=1024*512
romimage "normal"
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE=0x19000
option COREBOOT_EXTRA_VERSION=".0-normal"
payload __PAYLOAD__
end
romimage "fallback"
option USE_FALLBACK_IMAGE=1
option ROM_IMAGE_SIZE=0x19000
option COREBOOT_EXTRA_VERSION=".0-fallback"
payload __PAYLOAD__
end
Index: targets/gigabyte/m57sli/Config-abuild.lb
===================================================================
--- targets/gigabyte/m57sli/Config-abuild.lb
(.../branches/upstream/coreboot-v2)
+++ targets/gigabyte/m57sli/Config-abuild.lb (.../trunk/coreboot-v2)
@@ -8,6 +8,7 @@
option HOSTCC="CROSS_HOSTCC"
__COMPRESSION__
+__LOGLEVEL__
romimage "normal"
option USE_FAILOVER_IMAGE=0
Index: targets/gigabyte/ga_2761gxdk/Config-abuild.lb
===================================================================
--- targets/gigabyte/ga_2761gxdk/Config-abuild.lb
(.../branches/upstream/coreboot-v2)
+++ targets/gigabyte/ga_2761gxdk/Config-abuild.lb (.../trunk/coreboot-v2)
@@ -27,6 +27,7 @@
option HOSTCC="CROSS_HOSTCC"
__COMPRESSION__
+__LOGLEVEL__
option ROM_SIZE = 512*1024
Index: targets/digitallogic/msm586seg/Config-abuild.lb
===================================================================
--- targets/digitallogic/msm586seg/Config-abuild.lb
(.../branches/upstream/coreboot-v2)
+++ targets/digitallogic/msm586seg/Config-abuild.lb (.../trunk/coreboot-v2)
@@ -6,6 +6,7 @@
option HOSTCC="CROSS_HOSTCC"
__COMPRESSION__
+__LOGLEVEL__
romimage "fallback"
option FALLBACK_SIZE = 256 * 1024
Index: targets/emulation/qemu-x86/Config-abuild.lb
===================================================================
--- targets/emulation/qemu-x86/Config-abuild.lb
(.../branches/upstream/coreboot-v2)
+++ targets/emulation/qemu-x86/Config-abuild.lb (.../trunk/coreboot-v2)
@@ -6,6 +6,7 @@
option HOSTCC="CROSS_HOSTCC"
__COMPRESSION__
+__LOGLEVEL__
option ROM_SIZE=256*1024
Index: targets/technologic/ts5300/Config-abuild.lb
===================================================================
--- targets/technologic/ts5300/Config-abuild.lb
(.../branches/upstream/coreboot-v2)
+++ targets/technologic/ts5300/Config-abuild.lb (.../trunk/coreboot-v2)
@@ -6,6 +6,7 @@
option HOSTCC="CROSS_HOSTCC"
__COMPRESSION__
+__LOGLEVEL__
romimage "fallback"
option FALLBACK_SIZE = 256 * 1024
Index: targets/amd/pistachio/Config-abuild.lb
===================================================================
--- targets/amd/pistachio/Config-abuild.lb
(.../branches/upstream/coreboot-v2)
+++ targets/amd/pistachio/Config-abuild.lb (.../trunk/coreboot-v2)
@@ -8,6 +8,7 @@
option HOSTCC="CROSS_HOSTCC"
__COMPRESSION__
+__LOGLEVEL__
option ROM_SIZE=1024*1024
romimage "normal"
Index: targets/amd/dbm690t/Config-abuild.lb
===================================================================
--- targets/amd/dbm690t/Config-abuild.lb
(.../branches/upstream/coreboot-v2)
+++ targets/amd/dbm690t/Config-abuild.lb (.../trunk/coreboot-v2)
@@ -8,6 +8,7 @@
option HOSTCC="CROSS_HOSTCC"
__COMPRESSION__
+__LOGLEVEL__
option ROM_SIZE=1024*1024
romimage "normal"
Index: targets/amd/serengeti_cheetah/Config-abuild.lb
===================================================================
--- targets/amd/serengeti_cheetah/Config-abuild.lb
(.../branches/upstream/coreboot-v2)
+++ targets/amd/serengeti_cheetah/Config-abuild.lb (.../trunk/coreboot-v2)
@@ -8,6 +8,7 @@
option HOSTCC="CROSS_HOSTCC"
__COMPRESSION__
+__LOGLEVEL__
romimage "normal"
option USE_FAILOVER_IMAGE=0
Index: targets/amd/serengeti_cheetah_fam10/Config-abuild.lb
===================================================================
--- targets/amd/serengeti_cheetah_fam10/Config-abuild.lb
(.../branches/upstream/coreboot-v2)
+++ targets/amd/serengeti_cheetah_fam10/Config-abuild.lb
(.../trunk/coreboot-v2)
@@ -8,6 +8,7 @@
option HOSTCC="CROSS_HOSTCC"
__COMPRESSION__
+__LOGLEVEL__
option ROM_SIZE=1024*1024
Index: targets/rca/rm4100/Config-abuild.lb
===================================================================
--- targets/rca/rm4100/Config-abuild.lb (.../branches/upstream/coreboot-v2)
+++ targets/rca/rm4100/Config-abuild.lb (.../trunk/coreboot-v2)
@@ -26,6 +26,7 @@
option HOSTCC="CROSS_HOSTCC"
__COMPRESSION__
+__LOGLEVEL__
romimage "fallback"
option USE_FALLBACK_IMAGE = 1
Index: targets/iei/juki-511p/Config-abuild.lb
===================================================================
--- targets/iei/juki-511p/Config-abuild.lb
(.../branches/upstream/coreboot-v2)
+++ targets/iei/juki-511p/Config-abuild.lb (.../trunk/coreboot-v2)
@@ -6,6 +6,7 @@
option HOSTCC="CROSS_HOSTCC"
__COMPRESSION__
+__LOGLEVEL__
option ROM_SIZE=256*1024
###
Index: targets/tyan/s2912/Config-abuild.lb
===================================================================
--- targets/tyan/s2912/Config-abuild.lb (.../branches/upstream/coreboot-v2)
+++ targets/tyan/s2912/Config-abuild.lb (.../trunk/coreboot-v2)
@@ -8,6 +8,7 @@
option HOSTCC="CROSS_HOSTCC"
__COMPRESSION__
+__LOGLEVEL__
romimage "normal"
option USE_FAILOVER_IMAGE=0
Index: targets/tyan/s2912_fam10/Config-abuild.lb
===================================================================
--- targets/tyan/s2912_fam10/Config-abuild.lb
(.../branches/upstream/coreboot-v2)
+++ targets/tyan/s2912_fam10/Config-abuild.lb (.../trunk/coreboot-v2)
@@ -26,6 +26,7 @@
option HOSTCC="CROSS_HOSTCC"
__COMPRESSION__
+__LOGLEVEL__
romimage "normal"
option USE_FAILOVER_IMAGE=0
Index: targets/tyan/s2895/Config-abuild.lb
===================================================================
--- targets/tyan/s2895/Config-abuild.lb (.../branches/upstream/coreboot-v2)
+++ targets/tyan/s2895/Config-abuild.lb (.../trunk/coreboot-v2)
@@ -8,6 +8,7 @@
option HOSTCC="CROSS_HOSTCC"
__COMPRESSION__
+__LOGLEVEL__
romimage "normal"
option USE_FAILOVER_IMAGE=0
Index: targets/via/epia-m/Config-abuild.lb
===================================================================
--- targets/via/epia-m/Config-abuild.lb (.../branches/upstream/coreboot-v2)
+++ targets/via/epia-m/Config-abuild.lb (.../trunk/coreboot-v2)
@@ -6,6 +6,7 @@
option HOSTCC="CROSS_HOSTCC"
__COMPRESSION__
+__LOGLEVEL__
option ROM_SIZE=256*1024
Index: targets/via/epia-cn/Config-abuild.lb
===================================================================
--- targets/via/epia-cn/Config-abuild.lb
(.../branches/upstream/coreboot-v2)
+++ targets/via/epia-cn/Config-abuild.lb (.../trunk/coreboot-v2)
@@ -8,6 +8,7 @@
option HOSTCC="CROSS_HOSTCC"
__COMPRESSION__
+__LOGLEVEL__
option ROM_SIZE=512*1024
Index: targets/via/pc2500e/Config-abuild.lb
===================================================================
--- targets/via/pc2500e/Config-abuild.lb
(.../branches/upstream/coreboot-v2)
+++ targets/via/pc2500e/Config-abuild.lb (.../trunk/coreboot-v2)
@@ -26,6 +26,7 @@
option HOSTCC = "CROSS_HOSTCC"
__COMPRESSION__
+__LOGLEVEL__
option ROM_SIZE = 512 * 1024
Index: targets/msi/ms7135/Config-abuild.lb
===================================================================
--- targets/msi/ms7135/Config-abuild.lb (.../branches/upstream/coreboot-v2)
+++ targets/msi/ms7135/Config-abuild.lb (.../trunk/coreboot-v2)
@@ -8,6 +8,7 @@
option HOSTCC="CROSS_HOSTCC"
__COMPRESSION__
+__LOGLEVEL__
romimage "normal"
option USE_FAILOVER_IMAGE=0
Index: targets/msi/ms9282/Config-abuild.lb
===================================================================
--- targets/msi/ms9282/Config-abuild.lb (.../branches/upstream/coreboot-v2)
+++ targets/msi/ms9282/Config-abuild.lb (.../trunk/coreboot-v2)
@@ -8,6 +8,7 @@
option HOSTCC="CROSS_HOSTCC"
__COMPRESSION__
+__LOGLEVEL__
romimage "normal"
option USE_FALLBACK_IMAGE=0
Index: targets/msi/ms9185/Config-abuild.lb
===================================================================
--- targets/msi/ms9185/Config-abuild.lb (.../branches/upstream/coreboot-v2)
+++ targets/msi/ms9185/Config-abuild.lb (.../trunk/coreboot-v2)
@@ -8,6 +8,7 @@
option HOSTCC="CROSS_HOSTCC"
__COMPRESSION__
+__LOGLEVEL__
romimage "normal"
option USE_FALLBACK_IMAGE=0
Index: targets/msi/ms7260/Config-abuild.lb
===================================================================
--- targets/msi/ms7260/Config-abuild.lb (.../branches/upstream/coreboot-v2)
+++ targets/msi/ms7260/Config-abuild.lb (.../trunk/coreboot-v2)
@@ -26,6 +26,7 @@
option HOSTCC="CROSS_HOSTCC"
__COMPRESSION__
+__LOGLEVEL__
romimage "normal"
option USE_FAILOVER_IMAGE = 0
Index: targets/arima/hdama/Config-abuild.lb
===================================================================
--- targets/arima/hdama/Config-abuild.lb
(.../branches/upstream/coreboot-v2)
+++ targets/arima/hdama/Config-abuild.lb (.../trunk/coreboot-v2)
@@ -8,6 +8,7 @@
option HOSTCC="CROSS_HOSTCC"
__COMPRESSION__
+__LOGLEVEL__
option ROM_SIZE=512*1024
Index: targets/jetway/j7f24/Config-abuild.lb
===================================================================
--- targets/jetway/j7f24/Config-abuild.lb
(.../branches/upstream/coreboot-v2)
+++ targets/jetway/j7f24/Config-abuild.lb (.../trunk/coreboot-v2)
@@ -8,6 +8,7 @@
option HOSTCC="CROSS_HOSTCC"
__COMPRESSION__
+__LOGLEVEL__
option ROM_SIZE=512*1024
Index: targets/technexion/tim8690/Config-abuild.lb
===================================================================
--- targets/technexion/tim8690/Config-abuild.lb
(.../branches/upstream/coreboot-v2)
+++ targets/technexion/tim8690/Config-abuild.lb (.../trunk/coreboot-v2)
@@ -8,6 +8,7 @@
option HOSTCC="CROSS_HOSTCC"
__COMPRESSION__
+__LOGLEVEL__
romimage "normal"
option USE_FALLBACK_IMAGE=0
Index: targets/ibm/e326/Config-abuild.lb
===================================================================
--- targets/ibm/e326/Config-abuild.lb (.../branches/upstream/coreboot-v2)
+++ targets/ibm/e326/Config-abuild.lb (.../trunk/coreboot-v2)
@@ -8,6 +8,7 @@
option HOSTCC="CROSS_HOSTCC"
__COMPRESSION__
+__LOGLEVEL__
option ROM_SIZE=512*1024
Index: targets/nvidia/l1_2pvv/Config-abuild.lb
===================================================================
--- targets/nvidia/l1_2pvv/Config-abuild.lb
(.../branches/upstream/coreboot-v2)
+++ targets/nvidia/l1_2pvv/Config-abuild.lb (.../trunk/coreboot-v2)
@@ -8,6 +8,7 @@
option HOSTCC="CROSS_HOSTCC"
__COMPRESSION__
+__LOGLEVEL__
romimage "normal"
option USE_FAILOVER_IMAGE=0
Index: targets/asus/a8n_e/Config-abuild.lb
===================================================================
--- targets/asus/a8n_e/Config-abuild.lb (.../branches/upstream/coreboot-v2)
+++ targets/asus/a8n_e/Config-abuild.lb (.../trunk/coreboot-v2)
@@ -8,6 +8,7 @@
option HOSTCC="CROSS_HOSTCC"
__COMPRESSION__
+__LOGLEVEL__
romimage "normal"
option USE_FAILOVER_IMAGE=0
Index: util/abuild/abuild
===================================================================
--- util/abuild/abuild (.../branches/upstream/coreboot-v2)
+++ util/abuild/abuild (.../trunk/coreboot-v2)
@@ -52,6 +52,9 @@
# stackprotect mode enabled by -ns option.
stackprotect=false
+# loglevel changed with -l / --loglevel option
+loglevel=default
+
ARCH=`uname -m | sed -e s/i.86/i386/ -e s/sun4u/sparc64/ \
-e s/i86pc/i386/ \
-e s/arm.*/arm/ -e s/sa110/arm/ -e s/x86_64/amd64/ \
@@ -154,6 +157,7 @@
option HOSTCC="CROSS_HOSTCC"
__COMPRESSION__
+__LOGLEVEL__
EOF
if [ "$TARCH" == i386 ] ; then
@@ -185,6 +189,14 @@
) > $TARGET/Config-${VENDOR}_${MAINBOARD}.lb
fi
+ if [ "$loglevel" != "default" ]; then
+ LOGLEVEL1="option MAXIMUM_CONSOLE_LOGLEVEL=$loglevel"
+ LOGLEVEL2="option DEFAULT_CONSOLE_LOGLEVEL=$loglevel"
+ else
+ LOGLEVEL1="# no loglevel override"
+ LOGLEVEL2=""
+ fi
+
if [ "`which lzma`" != "" -a "$PAYLOAD" != /dev/null ]; then
COMPRESSION="option CONFIG_COMPRESSED_PAYLOAD_LZMA=1"
else
@@ -199,6 +211,8 @@
-e s:CROSS_PREFIX:"$CROSS_COMPILE":g \
-e s:CROSS_HOSTCC:"$HOSTCC":g \
-e s:__COMPRESSION__:"$COMPRESSION":g \
+ -e s:__LOGLEVEL__:"$LOGLEVEL1"\
+"$LOGLEVEL2":g \
$TARGET/Config-${VENDOR}_${MAINBOARD}.lb.pre >
$TARGET/Config-${VENDOR}_${MAINBOARD}.lb
printf " ok\n"
}
@@ -573,11 +587,11 @@
getoptbrand="`getopt -V`"
if [ "${getoptbrand:0:6}" == "getopt" ]; then
# Detected GNU getopt that supports long options.
- args=`getopt -l
version,verbose,help,all,target:,broken,payloads:,test,cpus:,silent,xml,config
Vvhat:bp:Tc:sxC -- "$@"`
+ args=`getopt -l
version,verbose,help,all,target:,broken,payloads:,test,cpus:,silent,xml,config,loglevel
Vvhat:bp:Tc:sxCl: -- "$@"`
eval set "$args"
else
# Detected non-GNU getopt
- args=`getopt Vvhat:bp:Tc:sxC $*`
+ args=`getopt Vvhat:bp:Tc:sxCl: $*`
set -- $args
fi
@@ -603,6 +617,7 @@
-ns|--nostackprotect) shift; stackprotect=true;;
-sb|--scan-build) shift; scanbuild=true;;
-C|--config) shift; configureonly=1;;
+ -l|--loglevel) shift; loglevel="$1"; shift;;
--) shift; break;;
-*) printf "Invalid option\n\n"; myhelp; exit 1;;
*) break;;
Index: src/arch/i386/boot/acpigen.c
===================================================================
--- src/arch/i386/boot/acpigen.c
(.../svn://[email protected]/coresystems/i945/branches/upstream/coreboot-v2/src/arch/i386/boot/acpigen.c)
(Revision 1486)
+++ src/arch/i386/boot/acpigen.c (.../src/arch/i386/boot/acpigen.c)
(Arbeitskopie)
@@ -260,3 +260,21 @@
acpigen_patch_len(len - 1);
return len;
}
+
+int acpigen_write_PSD_package(u32 domain, u32 numprocs, PSD_coord coordtype)
+{
+ int len, lenh, lenp;
+ lenh = acpigen_write_name("_PSD");
+ lenp = acpigen_write_package(1);
+ len = acpigen_write_package(5);
+ len += acpigen_write_byte(5); // 5 values
+ len += acpigen_write_byte(0); // revision 0
+ len += acpigen_write_dword(domain);
+ len += acpigen_write_dword(coordtype);
+ len += acpigen_write_dword(numprocs);
+ acpigen_patch_len(len-1);
+ len += lenp;
+ acpigen_patch_len(len-1);
+ return len + lenh;
+}
+
Index: src/arch/i386/include/arch/acpigen.h
===================================================================
--- src/arch/i386/include/arch/acpigen.h
(.../svn://[email protected]/coresystems/i945/branches/upstream/coreboot-v2/src/arch/i386/include/arch/acpigen.h)
(Revision 1486)
+++ src/arch/i386/include/arch/acpigen.h
(.../src/arch/i386/include/arch/acpigen.h) (Arbeitskopie)
@@ -40,5 +40,7 @@
int acpigen_write_empty_PCT(void);
int acpigen_write_PSS_package(u32 coreFreq, u32 power, u32 transLat, u32
busmLat,
u32 control, u32 status);
+typedef enum { SW_ALL=0xfc, SW_ANY=0xfd, HW_ALL=0xfe } PSD_coord;
+int acpigen_write_PSD_package(u32 domain, u32 numprocs, PSD_coord coordtype);
int acpigen_write_processor(u8 cpuindex, u32 pblock_addr, u8 pblock_len);
#endif
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