This continues the doco attempt. This also mentions some ideas on the new booting setup for v2. The latest changes will remove all need for people to do math. Signed-off-by: Ronald G. Minnich Index: LinuxBIOS-AMD64.tex =================================================================== --- LinuxBIOS-AMD64.tex (revision 4177) +++ LinuxBIOS-AMD64.tex (working copy) @@ -1687,7 +1687,128 @@ \subsubsection{boot sequence} No significant change from romcc code, except that the CAR code has to set up a stack. \subsection{failover} +Failover is the newest way to lay out a ROM. The choice of which image to run is removed from the fallback image and moved into a small, standalone piece of code. The code is simple enough to show here: +\begin{verbatim} +static unsigned long main(unsigned long bist) +{ + if (do_normal_boot()) + goto normal_image; + else + goto fallback_image; +normal_image: + __asm__ __volatile__("jmp __normal_image" : : "a" (bist) : ); + +cpu_reset: + __asm__ __volatile__("jmp __cpu_reset" : : "a" (bist) : ); + +fallback_image: + return bist; +} + +\end{verbatim} +Some motherboards have a more complex bus structure (e.g. Opteron). In those cases, the failover can be more complex, as it requires some hardware initialization to work correctly. As of this writing (April 2009), these boards have their own failover: +\begin{quote} +./src/mainboard/iei/nova4899r/failover.c +./src/mainboard/emulation/qemu-x86/failover.c +./src/mainboard/supermicro/x6dhr_ig/failover.c +./src/mainboard/supermicro/x6dai_g/failover.c +./src/mainboard/supermicro/x6dhe_g2/failover.c +./src/mainboard/supermicro/x6dhr_ig2/failover.c +./src/mainboard/supermicro/x6dhe_g/failover.c +./src/mainboard/dell/s1850/failover.c +./src/mainboard/intel/xe7501devkit/failover.c +./src/mainboard/intel/jarrell/failover.c +./src/mainboard/olpc/btest/failover.c +./src/mainboard/olpc/rev_a/failover.c +./src/mainboard/via/epia-m/failover.c +\end{quote} +Here is one of the more complicated ones: +\begin{verbatim} +static unsigned long main(unsigned long bist) +{ + /* Did just the cpu reset? */ + if (memory_initialized()) { + if (last_boot_normal()) { + goto normal_image; + } else { + goto cpu_reset; + } + } + + /* This is the primary cpu how should I boot? */ + else if (do_normal_boot()) { + goto normal_image; + } + else { + goto fallback_image; + } + normal_image: + asm volatile ("jmp __normal_image" + : /* outputs */ + : "a" (bist) /* inputs */ + : /* clobbers */ + ); + cpu_reset: + asm volatile ("jmp __cpu_reset" + : /* outputs */ + : "a"(bist) /* inputs */ + : /* clobbers */ + ); + fallback_image: + return bist; +} + +\end{verbatim} +They're not that different, in fact. So why are there different copies all over the tree? Simple: code inclusion. Most of the failover.c are different because they include different bits of code. Here is a key reason for killing C code inclusion in the tree. +\subsubsection{how it is built} +There two additional config variables: +\begin{itemize} +\item HAVE\_FAILOVER\_IMAGE Has to be defined when certain files are included. +\item USE\_FAILOVER\_IMAGE Enables the use of the failover image +\end{itemize} +Confusingly enough, almost all the uses of these two variables are either nested or both required to be set, e.g. +The fallback and normal builds are the same. The target config has a new clause that looks like this: +\begin{verbatim} +romimage "failover" + option USE_FAILOVER_IMAGE=1 + option USE_FALLBACK_IMAGE=0 + option ROM_IMAGE_SIZE=FAILOVER_SIZE + option XIP_ROM_SIZE=FAILOVER_SIZE + option COREBOOT_EXTRA_VERSION="\$(shell cat ../../VERSION)\_Failover" +end +\end{verbatim} +This new section uses some constructs not yet discussed in detail. XIP\_ROM\_SIZE just refers to the +fact that the failover code is eXecute In Place, i.e. not copied to ROM. Of course, the ROM part of normal/fallback is as well, so the usage of XIP here is somewhat confusinh. Finally, the USE\_FAILOVER\_IMAGE variable is set, which changes code compilation in a few places. If we just consider non-mainbard files, there are: +\begin{verbatim} +src/cpu/amd/car/cache_as_ram.inc +src/arch/i386/Config.lb +\end{verbatim} +For the cache\_as\_ram.inc file, the changes relate to the fact that failover code sets up CAR, so that fallback code need not. + +For the Config.lb, several aspects of build change. +When USE\_FAILOVER\_IMAGE, entry into both normal and fallback bios images is via a 32-bit entry point (when not defined, entry into fallback is a 16-entry point at the power-on reset vector). +\subsubsection{layout} +Failover.c becomes the new bootblock at the top of memory. It calls either normal or fallback. The address of normal and fallback is determined by ldscript magic. +\subsubsection{boot sequence} +failover.c tests a few variables and the calls the normal or fallback payload depending on those variables; usually they are CMOS settings. +\subsection{Proposed new image forat} +The new image format will use seperate compilation -- no C code included! -- on all files. + +The new design has a few key goals: +\begin{itemize} +\item Always use a bootblock (currently called failover). +The name failover.c, being utterly obscure, will not be used; instead, we will name the file bootblock.c. Instead of having a different copy for each mainboard, we can have just one copy. +\item Always use seperate compilation +\item Always use printk etc. in the ROM code +\item (longer term) from the bootblock, always use cbfs to locate the normal/fallback etc. code. This code will be XIP. +\end{itemize} + +\subsubsection{how it is built} +For now, since we are still using the config tool, we'll need a new command: bootblockobject, which creates a list of files to be included in the bootblock. Not a lot else will have to change. We are going to move to using the v3 CAR code assembly code (one or two files at most, instead of many) and, instead of the thicket of little ldscript files, one ldscript file. This strategy is subject to modification as events dictate. +\subsubsection{layout} +Almost the same, for now, as the current failover code. +\subsubsection{boot sequence} % % 14 Glossary %