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Hash: SHA1
Hi,
This will be my first contribution to the coreboot project.
I have a bunch of HP xw8000 workstations lying around and I want to give
it a try.
This patch hopefully adds support for the E7505 northbridge and the Xeon
(F2 model Pentium 4 like) processor to inteltool. Everything comes
directly from Intel's datasheets.
Please review it.
Regards,
- --
Raphaël Doursenaud
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Version: GnuPG v1.4.9 (GNU/Linux)
Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org
iEYEARECAAYFAknvGzAACgkQaZKmNAdXaVWUwwCgrgOMpBn/J6hFzm13DCEc7jME
C/gAoIvfpT/f1vC1XFjnZ+n04S5jtBUC
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diff -ruN inteltool/cpu.c inteltool.mod/cpu.c
--- inteltool/cpu.c 2009-04-22 15:06:24.000000000 +0200
+++ inteltool.mod/cpu.c 2009-04-22 14:58:13.000000000 +0200
@@ -95,6 +95,189 @@
char *name;
} msr_entry_t;
+ static const msr_entry_t modelf2x_global_msrs[] = {
+ { 0x0000, "IA32_P5_MC_ADDR" },
+ { 0x0001, "IA32_P5_MC_TYPE" },
+ { 0x0017, "IA32_PLATFORM_ID" },
+ { 0x002a, "MSR_EBC_HARD_POWERON" },
+ { 0x002b, "MSR_EBC_SOFT_POWERON" },
+ { 0x002c, "MSR_EBC_FREQUENCY_ID" },
+ //{ 0x0079, "IA32_BIOS_UPDT_TRIG" }, // Seems to be RO
+ { 0x019c, "IA32_THERM_STATUS" },
+ { 0x01a0, "IA32_MISC_ENABLES" },
+ { 0x0200, "IA32_MTRR_PHYSBASE0" },
+ { 0x0201, "IA32_MTRR_PHYSMASK0" },
+ { 0x0202, "IA32_MTRR_PHYSBASE1" },
+ { 0x0203, "IA32_MTRR_PHYSMASK1" },
+ { 0x0204, "IA32_MTRR_PHYSBASE2" },
+ { 0x0205, "IA32_MTRR_PHYSMASK2" },
+ { 0x0206, "IA32_MTRR_PHYSBASE3" },
+ { 0x0207, "IA32_MTRR_PHYSMASK3" },
+ { 0x0208, "IA32_MTRR_PHYSBASE4" },
+ { 0x0209, "IA32_MTRR_PHYSMASK4" },
+ { 0x020a, "IA32_MTRR_PHYSBASE5" },
+ { 0x020b, "IA32_MTRR_PHYSMASK5" },
+ { 0x020c, "IA32_MTRR_PHYSBASE6" },
+ { 0x020d, "IA32_MTRR_PHYSMASK6" },
+ { 0x020e, "IA32_MTRR_PHYSBASE7" },
+ { 0x020f, "IA32_MTRR_PHYSMASK7" },
+ { 0x0250, "IA32_MTRR_FIX64K_00000" },
+ { 0x0258, "IA32_MTRR_FIX16K_80000" },
+ { 0x0259, "IA32_MTRR_FIX16K_A0000" },
+ { 0x0268, "IA32_MTRR_FIX4K_C0000" },
+ { 0x0269, "IA32_MTRR_FIX4K_C8000" },
+ { 0x026a, "IA32_MTRR_FIX4K_D0000" },
+ { 0x026b, "IA32_MTRR_FIX4K_D8000" },
+ { 0x026c, "IA32_MTRR_FIX4K_E0000" },
+ { 0x026d, "IA32_MTRR_FIX4K_E8000" },
+ { 0x026e, "IA32_MTRR_FIX4K_F0000" },
+ { 0x026f, "IA32_MTRR_FIX4K_F8000" },
+ { 0x02ff, "IA32_MTRR_DEF_TYPE" },
+ { 0x0300, "MSR_BPU_COUNTER0" },
+ { 0x0301, "MSR_BPU_COUNTER1" },
+ { 0x0302, "MSR_BPU_COUNTER2" },
+ { 0x0303, "MSR_BPU_COUNTER3" },
+ { 0x0304, "MSR_MS_COUNTER0" },
+ { 0x0305, "MSR_MS_COUNTER1" },
+ { 0x0306, "MSR_MS_COUNTER2" },
+ { 0x0307, "MSR_MS_COUNTER3" },
+ { 0x0308, "MSR_FLAME_COUNTER0" },
+ { 0x0309, "MSR_FLAME_COUNTER1" },
+ { 0x030a, "MSR_FLAME_COUNTER2" },
+ { 0x030b, "MSR_FLAME_COUNTER3" },
+ { 0x030c, "MSR_IQ_COUNTER0" },
+ { 0x030d, "MSR_IQ_COUNTER1" },
+ { 0x030e, "MSR_IQ_COUNTER2" },
+ { 0x030f, "MSR_IQ_COUNTER3" },
+ { 0x0310, "MSR_IQ_COUNTER4" },
+ { 0x0311, "MSR_IQ_COUNTER5" },
+ { 0x0360, "MSR_BPU_CCCR0" },
+ { 0x0361, "MSR_BPU_CCCR1" },
+ { 0x0362, "MSR_BPU_CCCR2" },
+ { 0x0363, "MSR_BPU_CCCR3" },
+ { 0x0364, "MSR_MS_CCCR0" },
+ { 0x0365, "MSR_MS_CCCR1" },
+ { 0x0366, "MSR_MS_CCCR2" },
+ { 0x0367, "MSR_MS_CCCR3" },
+ { 0x0368, "MSR_FLAME_CCCR0" },
+ { 0x0369, "MSR_FLAME_CCCR1" },
+ { 0x036a, "MSR_FLAME_CCCR2" },
+ { 0x036b, "MSR_FLAME_CCCR3" },
+ { 0x036c, "MSR_IQ_CCCR0" },
+ { 0x036d, "MSR_IQ_CCCR1" },
+ { 0x036e, "MSR_IQ_CCCR2" },
+ { 0x036f, "MSR_IQ_CCCR3" },
+ { 0x0370, "MSR_IQ_CCCR4" },
+ { 0x0371, "MSR_IQ_CCCR5" },
+ { 0x03a0, "MSR_BSU_ESCR0" },
+ { 0x03a1, "MSR_BSU_ESCR1" },
+ { 0x03a2, "MSR_FSB_ESCR0" },
+ { 0x03a3, "MSR_FSB_ESCR1" },
+ { 0x03a4, "MSR_FIRM_ESCR0" },
+ { 0x03a5, "MSR_FIRM_ESCR1" },
+ { 0x03a6, "MSR_FLAME_ESCR0" },
+ { 0x03a7, "MSR_FLAME_ESCR1" },
+ { 0x03a8, "MSR_DAC_ESCR0" },
+ { 0x03a9, "MSR_DAC_ESCR1" },
+ { 0x03aa, "MSR_MOB_ESCR0" },
+ { 0x03ab, "MSR_MOB_ESCR1" },
+ { 0x03ac, "MSR_PMH_ESCR0" },
+ { 0x03ad, "MSR_PMH_ESCR1" },
+ { 0x03ae, "MSR_SAAT_ESCR0" },
+ { 0x03af, "MSR_SAAT_ESCR1" },
+ { 0x03b0, "MSR_U2L_ESCR0" },
+ { 0x03b1, "MSR_U2L_ESCR1" },
+ { 0x03b2, "MSR_BPU_ESCR0" },
+ { 0x03b3, "MSR_BPU_ESCR1" },
+ { 0x03b4, "MSR_IS_ESCR0" },
+ { 0x03b5, "MSR_IS_ESCR1" },
+ { 0x03b6, "MSR_ITLB_ESCR0" },
+ { 0x03b7, "MSR_ITLB_ESCR1" },
+ { 0x03b8, "MSR_CRU_ESCR0" },
+ { 0x03b9, "MSR_CRU_ESCR1" },
+ { 0x03ba, "MSR_IQ_ESCR0" },
+ { 0x03bb, "MSR_IQ_ESCR1" },
+ { 0x03bc, "MSR_RAT_ESCR0" },
+ { 0x03bd, "MSR_RAT_ESCR1" },
+ { 0x03be, "MSR_SSU_ESCR0" },
+ { 0x03c0, "MSR_MS_ESCR0" },
+ { 0x03c1, "MSR_MS_ESCR1" },
+ { 0x03c2, "MSR_TBPU_ESCR0" },
+ { 0x03c3, "MSR_TBPU_ESCR1" },
+ { 0x03c4, "MSR_TC_ESCR0" },
+ { 0x03c5, "MSR_TC_ESCR1" },
+ { 0x03c8, "MSR_IX_ESCR0" },
+ { 0x03c9, "MSR_IX_ESCR1" },
+ { 0x03ca, "MSR_ALF_ESCR0" },
+ { 0x03cb, "MSR_ALF_ESCR1" },
+ { 0x03cc, "MSR_CRU_ESCR2" },
+ { 0x03cd, "MSR_CRU_ESCR3" },
+ { 0x03e0, "MSR_CRU_ESCR4" },
+ { 0x03e1, "MSR_CRU_ESCR5" },
+ { 0x03f0, "MSR_TC_PRECISE_EVENT" },
+ { 0x03f1, "MSR_PEBS_ENABLE" },
+ { 0x03f2, "MSR_PEBS_MATRIX_VERT" },
+ { 0x0400, "IA32_MC0_CTL" },
+ { 0x0401, "IA32_MC0_STATUS" },
+ { 0x0402, "IA32_MC0_ADDR" },
+ { 0x0403, "IA32_MC0_MISC" },
+ { 0x0404, "IA32_MC1_CTL" },
+ { 0x0405, "IA32_MC1_STATUS" },
+ { 0x0406, "IA32_MC1_ADDR" },
+ //{ 0x0407, "IA32_MC1_MISC" }, // Seems to be RO
+ { 0x0408, "IA32_MC2_CTL" },
+ { 0x0409, "IA32_MC2_STATUS" },
+ //{ 0x040a, "IA32_MC2_ADDR" }, // Seems to be RO
+ //{ 0x040b, "IA32_MC2_MISC" }, // Seems to be RO
+ { 0x040c, "IA32_MC3_CTL" },
+ { 0x040d, "IA32_MC3_STATUS" },
+ { 0x040e, "IA32_MC3_ADDR" },
+ { 0x040f, "IA32_MC3_MISC" },
+ //{ 0x0410, "IA32_MC4_CTL" }, // Seems to be RO
+ //{ 0x0411, "IA32_MC4_STATUS" }, // Seems to be RO
+ //{ 0x0412, "IA32_MC4_ADDR" }, // Seems to be RO
+ //{ 0x0413, "IA32_MC4_MISC" } // Seems to be RO
+ };
+
+ static const msr_entry_t modelf2x_per_core_msrs[] = {
+ { 0x0010, "IA32_TIME_STAMP_COUNTER" },
+ { 0x001b, "IA32_APIC_BASE" },
+ { 0x008b, "IA32_BIOS_SIGN_ID" },
+ { 0x00fe, "IA32_MTRRCAP" },
+ { 0x0174, "IA32_SYSENTER_CS" },
+ { 0x0175, "IA32_SYSENTER_ESP" },
+ { 0x0176, "IA32_SYSENTER_EIP" },
+ { 0x017a, "IA32_MCG_STATUS" },
+ { 0x0180, "MSR_MCG_RAX" },
+ { 0x0181, "MSR_MCG_RBX" },
+ { 0x0182, "MSR_MCG_RCX" },
+ { 0x0183, "MSR_MCG_RDX" },
+ { 0x0184, "MSR_MCG_RSI" },
+ { 0x0185, "MSR_MCG_RDI" },
+ { 0x0186, "MSR_MCG_RBP" },
+ { 0x0187, "MSR_MCG_RSP" },
+ { 0x0188, "MSR_MCG_RFLAGS" },
+ { 0x0189, "MSR_MCG_RIP" },
+ { 0x018a, "MSR_MCG_MISC" },
+ { 0x018b, "MSR_MCG_RESERVED1" },
+ { 0x018c, "MSR_MCG_RESERVED2" },
+ { 0x018d, "MSR_MCG_RESERVED3" },
+ { 0x018e, "MSR_MCG_RESERVED4" },
+ { 0x018f, "MSR_MCG_RESERVED5" },
+ { 0x019a, "IA32_CLOCK_MODULATION" },
+ { 0x019b, "IA32_THERM_INTERRUPT" },
+ { 0x01d7, "MSR_LER_FROM_LIP" },
+ { 0x01d8, "MSR_LER_TO_LIP" },
+ { 0x01d9, "MSR_DEBUGCTLA" },
+ { 0x01da, "MSR_LASTBRANCH_TOS" },
+ { 0x01db, "MSR_LASTBRANCH_0" },
+ { 0x01dc, "MSR_LASTBRANCH_1" },
+ { 0x01dd, "MSR_LASTBRANCH_2" },
+ { 0x01de, "MSR_LASTBRANCH_3" },
+ { 0x0277, "IA32_CR_PAT" },
+ { 0x0600, "IA32_DS_AREA" },
+ };
+
static const msr_entry_t model6ex_global_msrs[] = {
{ 0x0017, "IA32_PLATFORM_ID" },
{ 0x002a, "EBL_CR_POWERON" },
@@ -257,6 +440,7 @@
} cpu_t;
cpu_t cpulist[] = {
+ { 0x00f20, modelf2x_global_msrs, ARRAY_SIZE(modelf2x_global_msrs), modelf2x_per_core_msrs, ARRAY_SIZE(modelf2x_per_core_msrs) },
{ 0x006e0, model6ex_global_msrs, ARRAY_SIZE(model6ex_global_msrs), model6ex_per_core_msrs, ARRAY_SIZE(model6ex_per_core_msrs) },
{ 0x006f0, model6fx_global_msrs, ARRAY_SIZE(model6fx_global_msrs), model6fx_per_core_msrs, ARRAY_SIZE(model6fx_per_core_msrs) },
};
diff -ruN inteltool/.dependencies inteltool.mod/.dependencies
--- inteltool/.dependencies 1970-01-01 01:00:00.000000000 +0100
+++ inteltool.mod/.dependencies 2009-04-22 14:58:35.000000000 +0200
@@ -0,0 +1,7 @@
+cpu.o: cpu.c inteltool.h
+gpio.o: gpio.c inteltool.h
+inteltool.o: inteltool.c inteltool.h
+memory.o: memory.c inteltool.h
+pcie.o: pcie.c inteltool.h
+powermgt.o: powermgt.c inteltool.h
+rootcmplx.o: rootcmplx.c inteltool.h
diff -ruN inteltool/inteltool.c inteltool.mod/inteltool.c
--- inteltool/inteltool.c 2009-04-22 15:06:24.000000000 +0200
+++ inteltool.mod/inteltool.c 2009-04-22 12:34:16.000000000 +0200
@@ -43,7 +43,8 @@
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH4, "ICH4" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH2, "ICH2" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH0, "ICH0" },
- { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH, "ICH" }
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH, "ICH" },
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7505, "E7505" }
};
#ifndef DARWIN
diff -ruN inteltool/inteltool.h inteltool.mod/inteltool.h
--- inteltool/inteltool.h 2009-04-22 15:06:24.000000000 +0200
+++ inteltool.mod/inteltool.h 2009-04-22 12:35:30.000000000 +0200
@@ -44,6 +44,7 @@
#define PCI_DEVICE_ID_INTEL_ICH8M 0x2815
#define PCI_DEVICE_ID_INTEL_82845 0x1a30
+#define PCI_DEVICE_ID_INTEL_E7505 0x2550
#define PCI_DEVICE_ID_INTEL_82945P 0x2770
#define PCI_DEVICE_ID_INTEL_82945GM 0x27a0
#define PCI_DEVICE_ID_INTEL_PM965 0x2a00
diff -ruN inteltool/memory.c inteltool.mod/memory.c
--- inteltool/memory.c 2009-04-22 15:06:24.000000000 +0200
+++ inteltool.mod/memory.c 2009-04-22 12:46:15.000000000 +0200
@@ -43,6 +43,7 @@
mchbar_phys = pci_read_long(nb, 0x48) & 0xfffffffe;
mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32;
break;
+ case PCI_DEVICE_ID_INTEL_E7505:
case 0x1234: // Dummy for non-existent functionality
printf("This northbrigde does not have MCHBAR.\n");
return 1;
diff -ruN inteltool/pcie.c inteltool.mod/pcie.c
--- inteltool/pcie.c 2009-04-22 15:06:24.000000000 +0200
+++ inteltool.mod/pcie.c 2009-04-22 12:48:05.000000000 +0200
@@ -42,6 +42,7 @@
epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe;
epbar_phys |= ((uint64_t)pci_read_long(nb, 0x44)) << 32;
break;
+ case PCI_DEVICE_ID_INTEL_E7505:
case 0x1234: // Dummy for non-existent functionality
printf("This northbrigde does not have EPBAR.\n");
return 1;
@@ -88,6 +89,7 @@
dmibar_phys = pci_read_long(nb, 0x68) & 0xfffffffe;
dmibar_phys |= ((uint64_t)pci_read_long(nb, 0x6c)) << 32;
break;
+ case PCI_DEVICE_ID_INTEL_E7505:
case 0x1234: // Dummy for non-existent functionality
printf("This northbrigde does not have DMIBAR.\n");
return 1;
@@ -136,6 +138,7 @@
pciexbar_reg = pci_read_long(nb, 0x60);
pciexbar_reg |= ((uint64_t)pci_read_long(nb, 0x64)) << 32;
break;
+ case PCI_DEVICE_ID_INTEL_E7505:
case 0x1234: // Dummy for non-existent functionality
printf("Error: This northbrigde does not have PCIEXBAR.\n");
return 1;
diff -ruN inteltool/powermgt.c inteltool.mod/powermgt.c
--- inteltool/powermgt.c 2009-04-22 15:06:24.000000000 +0200
+++ inteltool.mod/powermgt.c 2009-04-22 13:14:00.000000000 +0200
@@ -21,6 +21,52 @@
#include <stdio.h>
#include "inteltool.h"
+static const io_register_t ich4_pm_registers[] = {
+ { 0x00, 2, "PM1_STS" },
+ { 0x02, 2, "PM1_EN" },
+ { 0x04, 4, "PM1_CNT" },
+ { 0x08, 4, "PM1_TMR" },
+ { 0x0c, 1, "RESERVED" },
+ { 0x10, 4, "PROC_CNT" },
+#if DANGEROUS_REGISTERS
+ /* These registers return 0 on read, but reading them may cause
+ * the system to enter C2/C3/C4 state, which might hang the system.
+ */
+ { 0x14, 1, "LV2"},
+#endif
+ { 0x15, 2, "RESERVED" },
+ { 0x17, 9, "RESERVED" },
+ { 0x28, 4, "GPE0_STS" },
+ { 0x2C, 4, "GPE0_EN" },
+ { 0x30, 4, "SMI_EN" },
+ { 0x34, 4, "SMI_STS" },
+ { 0x38, 2, "ALT_GP_SMI_EN" },
+ { 0x3a, 2, "ALT_GP_SMI_STS" },
+ { 0x3c, 4, "RESERVED" },
+ { 0x40, 1, "MON_SMI_STS" },
+ { 0x42, 1, "RESERVED" },
+ { 0x44, 1, "DEVTRP_STS" },
+ { 0x48, 1, "TRP_EN" },
+ { 0x4c, 2, "BUS_ADDR_TRK" },
+ { 0x4e, 1, "BUS_CYCL_TRK" },
+ { 0x50, 1, "RESERVED" },
+ { 0x51, 15, "RESERVED" },
+ /* Here start the TCO registers */
+ { 0x60, 1, "TCO_RLD" },
+ { 0x61, 1, "TCO_TMR" },
+ { 0x62, 1, "TCO_DAT_IN" },
+ { 0x63, 1, "TCO_DAT_OUT" },
+ { 0x64, 2, "TCO1_STS" },
+ { 0x66, 2, "TCO2_STS" },
+ { 0x68, 2, "TCO1_CNT" },
+ { 0x6a, 2, "TCO2_CNT" },
+ { 0x6c, 2, "TCO_MESSAGE" },
+ { 0x6e, 1, "TCO_WDSTATUS" },
+ { 0x6f, 1, "RESERVED" },
+ { 0x70, 1, "SW_IRQ_GEN" },
+ { 0x71, 15, "RESERVED" },
+};
+
static const io_register_t ich7_pm_registers[] = {
{ 0x00, 2, "PM1_STS" },
{ 0x02, 2, "PM1_EN" },
@@ -154,6 +200,12 @@
printf("\n============= PMBASE ============\n\n");
switch (sb->device_id) {
+ case PCI_DEVICE_ID_INTEL_ICH4:
+ case PCI_DEVICE_ID_INTEL_ICH4M:
+ pmbase = pci_read_word(sb, 0x40) & 0xfffc;
+ pm_registers = ich4_pm_registers;
+ size = ARRAY_SIZE(ich4_pm_registers);
+ break;
case PCI_DEVICE_ID_INTEL_ICH7:
case PCI_DEVICE_ID_INTEL_ICH7M:
case PCI_DEVICE_ID_INTEL_ICH7DH:
--
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