Author: myles Date: 2009-05-01 00:45:41 +0200 (Fri, 01 May 2009) New Revision: 4240
Modified: trunk/coreboot-v2/src/arch/i386/boot/coreboot_table.c trunk/coreboot-v2/src/arch/i386/boot/tables.c trunk/coreboot-v2/src/arch/i386/include/arch/smp/mpspec.h trunk/coreboot-v2/src/arch/i386/smp/mpspec.c trunk/coreboot-v2/src/boot/hardwaremain.c trunk/coreboot-v2/src/boot/selfboot.c trunk/coreboot-v2/src/cpu/amd/dualcore/amd_sibling.c trunk/coreboot-v2/src/cpu/x86/lapic/lapic_cpu_init.c trunk/coreboot-v2/src/cpu/x86/pae/pgtbl.c trunk/coreboot-v2/src/include/cbfs.h trunk/coreboot-v2/src/lib/cbfs.c trunk/coreboot-v2/src/mainboard/tyan/s2892/cache_as_ram_auto.c trunk/coreboot-v2/src/mainboard/tyan/s2892/cmos.layout trunk/coreboot-v2/src/mainboard/tyan/s2892/irq_tables.c trunk/coreboot-v2/src/northbridge/amd/amdk8/amdk8.h trunk/coreboot-v2/src/northbridge/amd/amdk8/amdk8_acpi.c trunk/coreboot-v2/src/northbridge/amd/amdk8/debug.c trunk/coreboot-v2/src/northbridge/amd/amdk8/incoherent_ht.c trunk/coreboot-v2/src/northbridge/amd/amdk8/northbridge.c trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit.c trunk/coreboot-v2/src/pc80/keyboard.c trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_lpc.c trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_nic.c trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_sata.c trunk/coreboot-v2/util/cbfstool/cbfstool.h trunk/coreboot-v2/util/cbfstool/util.c trunk/coreboot-v2/util/options/build_opt_tbl.c Log: Remove warnings from compilation of the s2892 with and without CBFS. I didn't try to remove "defined but not used" warnings because there are too many ifdefs to be sure I wouldn't break something. For shadowed variable declarations I renamed the inner-most variable. The one in src/pc80/keyboard.c might need help. I didn't change the functionality but it looks like a bug. I boot tested it on s2892 and abuild tested it. Signed-off-by: Myles Watson <[email protected]> Acked-by: Ronald G. Minnich <[email protected]> Modified: trunk/coreboot-v2/src/arch/i386/boot/coreboot_table.c =================================================================== --- trunk/coreboot-v2/src/arch/i386/boot/coreboot_table.c 2009-04-30 16:46:12 UTC (rev 4239) +++ trunk/coreboot-v2/src/arch/i386/boot/coreboot_table.c 2009-04-30 22:45:41 UTC (rev 4240) @@ -428,7 +428,7 @@ printk_debug("Writing high table forward entry at 0x%08lx\n", low_table_end); head = lb_table_init(low_table_end); - lb_forward(head, rom_table_end); + lb_forward(head, (struct lb_header*)rom_table_end); lb_table_fini(head, 0); low_table_end = (unsigned long)head; Modified: trunk/coreboot-v2/src/arch/i386/boot/tables.c =================================================================== --- trunk/coreboot-v2/src/arch/i386/boot/tables.c 2009-04-30 16:46:12 UTC (rev 4239) +++ trunk/coreboot-v2/src/arch/i386/boot/tables.c 2009-04-30 22:45:41 UTC (rev 4240) @@ -66,7 +66,7 @@ { unsigned long low_table_start, low_table_end; unsigned long rom_table_start, rom_table_end; -#if HAVE_MP_TABLE == 1 +#if HAVE_MP_TABLE == 1 && HAVE_LOW_TABLES == 1 unsigned long new_low_table_end; #endif @@ -114,16 +114,16 @@ */ #if HAVE_ACPI_TABLES == 1 #if HAVE_HIGH_TABLES == 1 +#if HAVE_LOW_TABLES == 1 unsigned long high_rsdp=ALIGN(high_table_end, 16); + unsigned long rsdt_location=(unsigned long*)(((acpi_rsdp_t*)high_rsdp)->rsdt_address); + acpi_write_rsdp(rom_table_end, rsdt_location); + rom_table_end = ALIGN(ALIGN(rom_table_end, 16) + sizeof(acpi_rsdp_t), 16); +#endif if (high_tables_base) { high_table_end = write_acpi_tables(high_table_end); high_table_end = (high_table_end+1023) & ~1023; } -#if HAVE_LOW_TABLES == 1 - unsigned long rsdt_location=(unsigned long*)(((acpi_rsdp_t*)high_rsdp)->rsdt_address); - acpi_write_rsdp(rom_table_end, rsdt_location); - rom_table_end = ALIGN(ALIGN(rom_table_end, 16) + sizeof(acpi_rsdp_t), 16); -#endif #else #if HAVE_LOW_TABLES == 1 rom_table_end = write_acpi_tables(rom_table_end); Modified: trunk/coreboot-v2/src/arch/i386/include/arch/smp/mpspec.h =================================================================== --- trunk/coreboot-v2/src/arch/i386/include/arch/smp/mpspec.h 2009-04-30 16:46:12 UTC (rev 4239) +++ trunk/coreboot-v2/src/arch/i386/include/arch/smp/mpspec.h 2009-04-30 22:45:41 UTC (rev 4240) @@ -1,6 +1,7 @@ #ifndef __ASM_MPSPEC_H #define __ASM_MPSPEC_H +#include <device/device.h> /* * Structure definitions for SMP machines following the * Intel Multiprocessing Specification 1.1 and 1.4. Modified: trunk/coreboot-v2/src/arch/i386/smp/mpspec.c =================================================================== --- trunk/coreboot-v2/src/arch/i386/smp/mpspec.c 2009-04-30 16:46:12 UTC (rev 4239) +++ trunk/coreboot-v2/src/arch/i386/smp/mpspec.c 2009-04-30 22:45:41 UTC (rev 4240) @@ -1,5 +1,4 @@ #include <console/console.h> -#include <device/device.h> #include <device/path.h> #include <device/pci_ids.h> #include <cpu/cpu.h> @@ -23,9 +22,6 @@ void *smp_write_floating_table(unsigned long addr) { - struct intel_mp_floating *mf; - void *v; - /* 16 byte align the table address */ addr = (addr + 0xf) & (~0xf); return smp_write_floating_table_physaddr(addr, addr + SMP_FLOATING_TABLE_LEN); Modified: trunk/coreboot-v2/src/boot/hardwaremain.c =================================================================== --- trunk/coreboot-v2/src/boot/hardwaremain.c 2009-04-30 16:46:12 UTC (rev 4239) +++ trunk/coreboot-v2/src/boot/hardwaremain.c 2009-04-30 22:45:41 UTC (rev 4240) @@ -99,9 +99,9 @@ lb_mem = write_tables(); #if CONFIG_CBFS == 1 # if USE_FALLBACK_IMAGE == 1 - void (*pl)(void) = cbfs_load_payload(lb_mem, "fallback/payload"); + cbfs_load_payload(lb_mem, "fallback/payload"); # else - void (*pl)(void) = cbfs_load_payload(lb_mem, "normal/payload"); + cbfs_load_payload(lb_mem, "normal/payload"); # endif #else Modified: trunk/coreboot-v2/src/boot/selfboot.c =================================================================== --- trunk/coreboot-v2/src/boot/selfboot.c 2009-04-30 16:46:12 UTC (rev 4239) +++ trunk/coreboot-v2/src/boot/selfboot.c 2009-04-30 22:45:41 UTC (rev 4240) @@ -302,7 +302,6 @@ { struct segment *new; struct segment *ptr; - u8 *data; int datasize; struct cbfs_payload_segment *segment, *first_segment; memset(head, 0, sizeof(*head)); @@ -352,7 +351,7 @@ case PAYLOAD_SEGMENT_ENTRY: printk_info("Entry %p\n", (void *) ntohl((u32) segment->load_addr)); - *entry = (void *) ntohl((u32) segment->load_addr); + *entry = ntohl((u32) segment->load_addr); return 1; } segment++; @@ -392,15 +391,13 @@ offset = 0; for(ptr = head->next; ptr != head; ptr = ptr->next) { - unsigned long skip_bytes, read_bytes; unsigned char *dest, *middle, *end, *src; - byte_offset_t result; printk_debug("Loading Segment: addr: 0x%016lx memsz: 0x%016lx filesz: 0x%016lx\n", ptr->s_dstaddr, ptr->s_memsz, ptr->s_filesz); /* Compute the boundaries of the segment */ dest = (unsigned char *)(ptr->s_dstaddr); - src = ptr->s_srcaddr; + src = (unsigned char *)(ptr->s_srcaddr); /* Copy data from the initial buffer */ if (ptr->s_filesz) { @@ -451,13 +448,11 @@ } } return 1; - out: - return 0; } int selfboot(struct lb_memory *mem, struct cbfs_payload *payload) { - void *entry; + u32 entry=0; struct segment head; unsigned long bounce_buffer; @@ -481,11 +476,11 @@ /* Reset to booting from this image as late as possible */ boot_successful(); - printk_debug("Jumping to boot code at %p\n", entry); + printk_debug("Jumping to boot code at %x\n", entry); post_code(0xfe); /* Jump to kernel */ - jmp_to_elf_entry(entry, bounce_buffer); + jmp_to_elf_entry((void*)entry, bounce_buffer); return 1; out: Modified: trunk/coreboot-v2/src/cpu/amd/dualcore/amd_sibling.c =================================================================== --- trunk/coreboot-v2/src/cpu/amd/dualcore/amd_sibling.c 2009-04-30 16:46:12 UTC (rev 4239) +++ trunk/coreboot-v2/src/cpu/amd/dualcore/amd_sibling.c 2009-04-30 22:45:41 UTC (rev 4240) @@ -62,9 +62,6 @@ unsigned nb_cfg_54; int bsp_apic_id = lapicid(); // bsp apicid - int disable_siblings = !CONFIG_LOGICAL_CPUS; - - get_option(&disable_siblings, "dual_core"); //get the nodes number Modified: trunk/coreboot-v2/src/cpu/x86/lapic/lapic_cpu_init.c =================================================================== --- trunk/coreboot-v2/src/cpu/x86/lapic/lapic_cpu_init.c 2009-04-30 16:46:12 UTC (rev 4239) +++ trunk/coreboot-v2/src/cpu/x86/lapic/lapic_cpu_init.c 2009-04-30 22:45:41 UTC (rev 4240) @@ -252,8 +252,8 @@ } else { // for all APs, let use stack after pgtbl, 20480 is the pgtbl size for every cpu stack_end = 0x100000+(20480 + STACK_SIZE)*CONFIG_MAX_CPUS - (STACK_SIZE*index); -#if (0x100000+(20480 + STACK_SIZE)*CONFIG_MAX_CPU) > (CONFIG_LB_MEM_TOPK<<10) - #warning "We may need to increase CONFIG_LB_MEM_TOPK, it need to be more than (0x100000+(20480 + STACK_SIZE)*CONFIG_MAX_CPU)\n" +#if (0x100000+(20480 + STACK_SIZE)*CONFIG_MAX_CPUS) > (CONFIG_LB_MEM_TOPK<<10) + #warning "We may need to increase CONFIG_LB_MEM_TOPK, it need to be more than (0x100000+(20480 + STACK_SIZE)*CONFIG_MAX_CPUS)\n" #endif if(stack_end > (CONFIG_LB_MEM_TOPK<<10)) { printk_debug("start_cpu: Please increase the CONFIG_LB_MEM_TOPK more than %luK\n", stack_end>>10); Modified: trunk/coreboot-v2/src/cpu/x86/pae/pgtbl.c =================================================================== --- trunk/coreboot-v2/src/cpu/x86/pae/pgtbl.c 2009-04-30 16:46:12 UTC (rev 4239) +++ trunk/coreboot-v2/src/cpu/x86/pae/pgtbl.c 2009-04-30 22:45:41 UTC (rev 4240) @@ -59,11 +59,11 @@ pgtbl is too big, so use last one 1M before CONFIG_LB_MEM_TOP, otherwise for 8 way dual core with vga support will push stack and heap cross 0xa0000, and that region need to be used as vga font buffer. Please make sure set CONFIG_LB_MEM_TOPK=2048 in MB Config */ - struct pg_table *pgtbl = 0x100000; //1M + struct pg_table *pgtbl = (struct pg_table*)0x100000; //1M unsigned x_end = 0x100000 + sizeof(struct pg_table) * CONFIG_MAX_CPUS; -#if (0x100000+20480*CONFIG_MAX_CPU) > (CONFIG_LB_MEM_TOPK<<10) - #warning "We may need to increase CONFIG_LB_MEM_TOPK, it need to be more than (0x100000+20480*CONFIG_MAX_CPU)\n" +#if (0x100000+20480*CONFIG_MAX_CPUS) > (CONFIG_LB_MEM_TOPK<<10) + #warning "We may need to increase CONFIG_LB_MEM_TOPK, it need to be more than (0x100000+20480*CONFIG_MAX_CPUS)\n" #endif if(x_end > (CONFIG_LB_MEM_TOPK<<10)) { printk_debug("map_2M_page: Please increase the CONFIG_LB_MEM_TOPK more than %dK\n", x_end>>10); Modified: trunk/coreboot-v2/src/include/cbfs.h =================================================================== --- trunk/coreboot-v2/src/include/cbfs.h 2009-04-30 16:46:12 UTC (rev 4239) +++ trunk/coreboot-v2/src/include/cbfs.h 2009-04-30 22:45:41 UTC (rev 4240) @@ -49,6 +49,7 @@ #ifndef _CBFS_H_ #define _CBFS_H_ +#include <boot/coreboot_tables.h> /** These are standard values for the known compression alogrithms that coreboot knows about for stages and payloads. Of course, other LAR users can use whatever Modified: trunk/coreboot-v2/src/lib/cbfs.c =================================================================== --- trunk/coreboot-v2/src/lib/cbfs.c 2009-04-30 16:46:12 UTC (rev 4239) +++ trunk/coreboot-v2/src/lib/cbfs.c 2009-04-30 22:45:41 UTC (rev 4240) @@ -20,7 +20,6 @@ #include <types.h> #include <string.h> #include <console/console.h> -#include <boot/coreboot_tables.h> #include <cbfs.h> #ifndef CONFIG_BIG_ENDIAN Modified: trunk/coreboot-v2/src/mainboard/tyan/s2892/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2892/cache_as_ram_auto.c 2009-04-30 16:46:12 UTC (rev 4239) +++ trunk/coreboot-v2/src/mainboard/tyan/s2892/cache_as_ram_auto.c 2009-04-30 22:45:41 UTC (rev 4240) @@ -90,8 +90,6 @@ static void sio_setup(void) { - - unsigned value; uint32_t dword; uint8_t byte; @@ -102,7 +100,6 @@ dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0); dword |= (1<<0); pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword); - } void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) Modified: trunk/coreboot-v2/src/mainboard/tyan/s2892/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2892/cmos.layout 2009-04-30 16:46:12 UTC (rev 4239) +++ trunk/coreboot-v2/src/mainboard/tyan/s2892/cmos.layout 2009-04-30 22:45:41 UTC (rev 4240) @@ -46,7 +46,7 @@ 728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 reserved_memory +1000 24 r 0 reserved_memory1 Modified: trunk/coreboot-v2/src/mainboard/tyan/s2892/irq_tables.c =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2892/irq_tables.c 2009-04-30 16:46:12 UTC (rev 4239) +++ trunk/coreboot-v2/src/mainboard/tyan/s2892/irq_tables.c 2009-04-30 22:45:41 UTC (rev 4240) @@ -65,7 +65,7 @@ addr &= ~15; /* This table must be betweeen 0xf0000 & 0x100000 */ - printk_info("Writing IRQ routing tables to 0x%x...", addr); + printk_info("Writing IRQ routing tables to 0x%lx...", addr); pirq = (void *)(addr); v = (uint8_t *)(addr); Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/amdk8.h =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdk8/amdk8.h 2009-04-30 16:46:12 UTC (rev 4239) +++ trunk/coreboot-v2/src/northbridge/amd/amdk8/amdk8.h 2009-04-30 22:45:41 UTC (rev 4240) @@ -244,7 +244,6 @@ #include "raminit.h" //struct definitions -#if RAMINIT_SYSINFO==1 struct link_pair_st { device_t udev; uint32_t upos; @@ -267,9 +266,7 @@ uint32_t sblk; uint32_t sbbusn; } __attribute__((packed)); -#endif - #endif #endif /* AMDK8_H */ Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/amdk8_acpi.c =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdk8/amdk8_acpi.c 2009-04-30 16:46:12 UTC (rev 4239) +++ trunk/coreboot-v2/src/northbridge/amd/amdk8/amdk8_acpi.c 2009-04-30 22:45:41 UTC (rev 4240) @@ -218,8 +218,6 @@ } static int k8acpi_write_HT(void) { - device_t dev; - uint32_t dword; int len, lenp, i; len = acpigen_write_name("HCLK"); Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/debug.c =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdk8/debug.c 2009-04-30 16:46:12 UTC (rev 4239) +++ trunk/coreboot-v2/src/northbridge/amd/amdk8/debug.c 2009-04-30 22:45:41 UTC (rev 4240) @@ -3,6 +3,10 @@ * */ +#ifndef CACHE_AS_RAM_ADDRESS_DEBUG +#define CACHE_AS_RAM_ADDRESS_DEBUG 0 +#endif + static inline void print_debug_addr(const char *str, void *val) { #if CACHE_AS_RAM_ADDRESS_DEBUG == 1 Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/incoherent_ht.c =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdk8/incoherent_ht.c 2009-04-30 16:46:12 UTC (rev 4239) +++ trunk/coreboot-v2/src/northbridge/amd/amdk8/incoherent_ht.c 2009-04-30 22:45:41 UTC (rev 4240) @@ -11,6 +11,10 @@ #define K8_HT_FREQ_1G_SUPPORT 0 #endif +#ifndef RAMINIT_SYSINFO + #define RAMINIT_SYSINFO 0 +#endif + #ifndef K8_SCAN_PCI_BUS #define K8_SCAN_PCI_BUS 0 #endif @@ -79,7 +83,6 @@ static void ht_collapse_previous_enumeration(uint8_t bus, unsigned offset_unitid) { device_t dev; - uint32_t id; //actually, only for one HT device HT chain, and unitid is 0 #if HT_CHAIN_UNITID_BASE == 0 @@ -90,6 +93,7 @@ /* Check if is already collapsed */ if((!offset_unitid) || (offset_unitid && (!((HT_CHAIN_END_UNITID_BASE == 0) && (HT_CHAIN_END_UNITID_BASE <HT_CHAIN_UNITID_BASE))))) { + uint32_t id; dev = PCI_DEV(bus, 0, 0); id = pci_read_config32(dev, PCI_VENDOR_ID); if (!((id == 0xffffffff) || (id == 0x00000000) || @@ -556,7 +560,9 @@ } while (last_unitid != next_unitid ); +#if HT_CHAIN_END_UNITID_BASE != 0x20 out: +#endif end_of_chain: ; #if HT_CHAIN_END_UNITID_BASE != 0x20 Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/northbridge.c =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdk8/northbridge.c 2009-04-30 16:46:12 UTC (rev 4239) +++ trunk/coreboot-v2/src/northbridge/amd/amdk8/northbridge.c 2009-04-30 22:45:41 UTC (rev 4240) @@ -288,7 +288,7 @@ device_t goal_dev, unsigned goal_nodeid, unsigned goal_link) { struct resource *res; - unsigned nodeid, link; + unsigned nodeid, link=0; int result; res = 0; for(nodeid = 0; !res && (nodeid < FX_DEVS); nodeid++) { @@ -648,16 +648,16 @@ /* Is this register allocated? */ if ((base & 3) != 0) { unsigned nodeid, link; - device_t dev; + device_t reg_dev; nodeid = limit & 7; link = (limit >> 4) & 3; - dev = __f0_dev[nodeid]; - if (dev) { + reg_dev = __f0_dev[nodeid]; + if (reg_dev) { /* Reserve the resource */ - struct resource *resource; - resource = new_resource(dev, 0x100 + (reg | link)); - if (resource) { - resource->flags = 1; + struct resource *reg_resource; + reg_resource = new_resource(reg_dev, 0x100 + (reg | link)); + if (reg_resource) { + reg_resource->flags = 1; } } } @@ -1222,20 +1222,20 @@ /* Find which cpus are present */ cpu_bus = &dev->link[0]; for(i = 0; i < sysconf.nodes; i++) { - device_t dev, cpu; + device_t cpu_dev, cpu; struct device_path cpu_path; /* Find the cpu's pci device */ - dev = dev_find_slot(0, PCI_DEVFN(0x18 + i, 3)); - if (!dev) { + cpu_dev = dev_find_slot(0, PCI_DEVFN(0x18 + i, 3)); + if (!cpu_dev) { /* If I am probing things in a weird order * ensure all of the cpu's pci devices are found. */ - int j; + int local_j; device_t dev_f0; - for(j = 0; j <= 3; j++) { - dev = pci_probe_dev(NULL, dev_mc->bus, - PCI_DEVFN(0x18 + i, j)); + for(local_j = 0; local_j <= 3; local_j++) { + cpu_dev = pci_probe_dev(NULL, dev_mc->bus, + PCI_DEVFN(0x18 + i, local_j)); } /* Ok, We need to set the links for that device. * otherwise the device under it will not be scanned @@ -1243,19 +1243,19 @@ dev_f0 = dev_find_slot(0, PCI_DEVFN(0x18+i,0)); if(dev_f0) { dev_f0->links = 3; - for(j=0;j<3;j++) { - dev_f0->link[j].link = j; - dev_f0->link[j].dev = dev_f0; + for(local_j=0;local_j<3;local_j++) { + dev_f0->link[local_j].link = local_j; + dev_f0->link[local_j].dev = dev_f0; } } } e0_later_single_core = 0; - if (dev && dev->enabled) { - j = pci_read_config32(dev, 0xe8); + if (cpu_dev && cpu_dev->enabled) { + j = pci_read_config32(cpu_dev, 0xe8); j = (j >> 12) & 3; // dev is func 3 - printk_debug(" %s siblings=%d\n", dev_path(dev), j); + printk_debug(" %s siblings=%d\n", dev_path(cpu_dev), j); if(nb_cfg_54) { // For e0 single core if nb_cfg_54 is set, apicid will be 0, 2, 4.... @@ -1308,7 +1308,7 @@ cpu = find_dev_path(cpu_bus, &cpu_path); /* Enable the cpu if I have the processor */ - if (dev && dev->enabled) { + if (cpu_dev && cpu_dev->enabled) { if (!cpu) { cpu = alloc_dev(cpu_bus, &cpu_path); } @@ -1318,7 +1318,7 @@ } /* Disable the cpu if I don't have the processor */ - if (cpu && (!dev || !dev->enabled)) { + if (cpu && (!cpu_dev || !cpu_dev->enabled)) { cpu->enabled = 0; } Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit.c =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit.c 2009-04-30 16:46:12 UTC (rev 4239) +++ trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit.c 2009-04-30 22:45:41 UTC (rev 4240) @@ -805,7 +805,6 @@ }; uint32_t map; - uint32_t dch; map = pci_read_config32(ctrl->f2, DRAM_BANK_ADDR_MAP); map &= ~(0xf << (index * 4)); @@ -1491,19 +1490,19 @@ /* Loop through and find a fast clock with a low latency */ for(index = 0; index < 3; index++, latency++) { - int value; + int spd_value; if ((latency < 2) || (latency > 4) || (!(latencies & (1 << latency)))) { continue; } - value = spd_read_byte(ctrl->channel0[i], latency_indicies[index]); - if (value < 0) { + spd_value = spd_read_byte(ctrl->channel0[i], latency_indicies[index]); + if (spd_value < 0) { goto hw_error; } /* Only increase the latency if we decreas the clock */ - if ((value >= min_cycle_time) && (value < new_cycle_time)) { - new_cycle_time = value; + if ((spd_value >= min_cycle_time) && (spd_value < new_cycle_time)) { + new_cycle_time = spd_value; new_latency = latency; } } @@ -1527,7 +1526,7 @@ int latencies; int latency; int index; - int value; + int spd_value; if (!(dimm_mask & (1 << i))) { continue; } @@ -1554,13 +1553,13 @@ } /* Read the min_cycle_time for this latency */ - value = spd_read_byte(ctrl->channel0[i], latency_indicies[index]); - if (value < 0) goto hw_error; + spd_value = spd_read_byte(ctrl->channel0[i], latency_indicies[index]); + if (spd_value < 0) goto hw_error; /* All is good if the selected clock speed * is what I need or slower. */ - if (value <= min_cycle_time) { + if (spd_value <= min_cycle_time) { continue; } /* Otherwise I have an error, disable the dimm */ Modified: trunk/coreboot-v2/src/pc80/keyboard.c =================================================================== --- trunk/coreboot-v2/src/pc80/keyboard.c 2009-04-30 16:46:12 UTC (rev 4239) +++ trunk/coreboot-v2/src/pc80/keyboard.c 2009-04-30 22:45:41 UTC (rev 4240) @@ -112,11 +112,11 @@ outb(0x60, 0x64); if (!kbc_input_buffer_empty()) return; outb(0x20, 0x60); /* send cmd: enable keyboard and IRQ 1 */ - u8 resend = 10; + u8 broken_resend = 10; if ((inb(0x64) & 0x01)) { regval = inb(0x60); } - --resend; + --broken_resend; } while (regval == 0xFE && resend > 0); /* clean up any junk that might have been in the keyboard */ Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_lpc.c =================================================================== --- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_lpc.c 2009-04-30 16:46:12 UTC (rev 4239) +++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_lpc.c 2009-04-30 22:45:41 UTC (rev 4240) @@ -171,7 +171,7 @@ pci_write_config32(dev, 0x44, 0xfed00001); hpet_address = pci_read_config32(dev, 0x44) & 0xfffffffe; - printk_debug("Enabling HPET @0x%x\n", hpet_address); + printk_debug("Enabling HPET @0x%lx\n", hpet_address); } unsigned pm_base=0; @@ -184,7 +184,7 @@ lpc_common_init(dev); pm_base = pci_read_config32(dev, 0x60) & 0xff00; - printk_info("%s: pm_base = %lx \n", __func__, pm_base); + printk_info("%s: pm_base = %x \n", __func__, pm_base); #if CK804_CHIP_REV==1 if (dev->bus->secondary != 1) Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_nic.c =================================================================== --- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_nic.c 2009-04-30 16:46:12 UTC (rev 4239) +++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_nic.c 2009-04-30 22:45:41 UTC (rev 4240) @@ -22,7 +22,7 @@ struct resource *res; res = find_resource(dev, 0x10); - base = res->base; + base = (uint8_t*)(unsigned long)res->base; #define NvRegPhyInterface 0xC0 #define PHY_RGMII 0x10000000 @@ -76,8 +76,8 @@ if (!eeprom_valid) { unsigned long mac_pos; mac_pos = 0xffffffd0; /* See romstrap.inc and romstrap.lds. */ - mac_l = readl(mac_pos) + nic_index; - mac_h = readl(mac_pos + 4); + mac_l = readl((uint8_t*)mac_pos) + nic_index; + mac_h = readl((uint8_t*)mac_pos + 4); } #if 1 /* Set that into NIC MMIO. */ Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_sata.c =================================================================== --- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_sata.c 2009-04-30 16:46:12 UTC (rev 4239) +++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_sata.c 2009-04-30 22:45:41 UTC (rev 4240) @@ -11,6 +11,10 @@ #include <device/pci_ops.h> #include "ck804.h" +#ifndef CK804_SATA_RESET_FOR_ATAPI +#define CK804_SATA_RESET_FOR_ATAPI 0 +#endif + #if CK804_SATA_RESET_FOR_ATAPI static void sata_com_reset(struct device *dev, unsigned reset) // reset = 1 : reset Modified: trunk/coreboot-v2/util/cbfstool/cbfstool.h =================================================================== --- trunk/coreboot-v2/util/cbfstool/cbfstool.h 2009-04-30 16:46:12 UTC (rev 4239) +++ trunk/coreboot-v2/util/cbfstool/cbfstool.h 2009-04-30 22:45:41 UTC (rev 4240) @@ -58,7 +58,7 @@ /* util.c */ int open_rom(struct rom *rom, const char *filename); int create_rom(struct rom *rom, const unsigned char *filename, int size, - const unsigned char *bootblockname, int bootblocksize, + const char *bootblockname, int bootblocksize, int align); int size_and_open(const char *filename, unsigned int *size); int copy_from_fd(int fd, void *ptr, int size); Modified: trunk/coreboot-v2/util/cbfstool/util.c =================================================================== --- trunk/coreboot-v2/util/cbfstool/util.c 2009-04-30 16:46:12 UTC (rev 4239) +++ trunk/coreboot-v2/util/cbfstool/util.c 2009-04-30 22:45:41 UTC (rev 4240) @@ -168,7 +168,7 @@ } int create_rom(struct rom *rom, const unsigned char *filename, - int romsize, const unsigned char *bootblockname, + int romsize, const char *bootblockname, int bootblocksize, int align) { unsigned char null = '\0'; @@ -226,7 +226,6 @@ unsigned int size; int fd = size_and_open(filename, &size); int ret; - struct cbfs_header tmp; if (fd == -1) return -1; Modified: trunk/coreboot-v2/util/options/build_opt_tbl.c =================================================================== --- trunk/coreboot-v2/util/options/build_opt_tbl.c 2009-04-30 16:46:12 UTC (rev 4239) +++ trunk/coreboot-v2/util/options/build_opt_tbl.c 2009-04-30 22:45:41 UTC (rev 4240) @@ -487,6 +487,7 @@ /* See if we want to output a C source file */ if(option) { + int err=0; strncpy(tmpfilename, dirname(option), TMPFILE_LEN); strncat(tmpfilename, TMPFILE_TEMPLATE, TMPFILE_LEN); tmpfile = mkstemp(tmpfilename); @@ -510,13 +511,13 @@ } /* write the array values */ for(i=0;i<(ct->size-1);i++) { - if(!(i%10)) fwrite("\n\t",1,2,fp); + if(!(i%10) && !err) err=fwrite("\n\t",1,2,fp); sprintf(buf,"0x%02x,",cmos_table[i]); - fwrite(buf,1,5,fp); + if(!err) err=fwrite(buf,1,5,fp); } /* write the end */ sprintf(buf,"0x%02x\n",cmos_table[i]); - fwrite(buf,1,4,fp); + if(!err) err=fwrite(buf,1,4,fp); if(!fwrite("};\n",1,3,fp)) { perror("Error - Could not write image file"); fclose(fp); -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
