On Fri, May 01, 2009 at 11:42:17PM +0200, Rudolf Marek wrote: > -----BEGIN PGP SIGNED MESSAGE----- > Hash: SHA1 > > Hi again, > > I'm attaching a rewritten version from VGA ROM, which mimics the BIOS init. > > Sadly enough it is still not hitting the all required regs to make powernow > working as it is with orig bios. > > The rest register spill is the captured IO as it was. The top of the file is > what bios is doing during the init. Just before it calls ax=0003 and exits > the rom. > > There is also one interresting place: > > <------>write_cr((read_cr(0x36) & ~0x30) | (0x3 << 4), 0x36);
VGA H/VSync off. > <------>write_cr((read_cr(0x30) & ~0x4), 0x30); Disable Power Now Signals in CRTC1, as can be read from public via docs. > <------>/* just read, hope compiler won't optimize that out */ > <------>tmp = inb(0x3da); > <------>tmp = inb(0x3ba); STAT1 (both colour and mono) > <------>outb(0x0, 0x3c0); STAT0 > > /* original bios has it but if I compile it in I get blank screen */ > //<---->tmp = inb(0x3da); > <------>tmp = inb(0x3ba); Halfway through the dump the vga device is set from mono to colour. > The bios is doing it exactly like this. But if I enable the inb(0x3da) I get > no > picture but monitors seems to have some signal. It works fine without those > inbs. Any idea what is doing the code? Hrm. This is the AR register accesses. They require a read from STAT1 for the internal counter to be reset and thus for correct read/write operations. Luc Verhaegen. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
