Author: linux_junkie Date: 2009-05-08 02:24:24 +0200 (Fri, 08 May 2009) New Revision: 4259
Modified: trunk/coreboot-v2/src/mainboard/rca/rm4100/Config.lb trunk/coreboot-v2/src/mainboard/thomson/ip1000/Config.lb Log: Set up PIRQs in mainboard Config.lb for IP1000 and RM4100 instead of using the ones in i82801xx_lpc.c. Signed-off-by: Joseph Smith <[email protected]> Acked-by: Myles Watson <[email protected]> Modified: trunk/coreboot-v2/src/mainboard/rca/rm4100/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/rca/rm4100/Config.lb 2009-05-08 00:19:13 UTC (rev 4258) +++ trunk/coreboot-v2/src/mainboard/rca/rm4100/Config.lb 2009-05-08 00:24:24 UTC (rev 4259) @@ -80,6 +80,15 @@ register "rom_address" = "0xfff00000" end chip southbridge/intel/i82801xx # Southbridge + register "pirqa_routing" = "0x07" + register "pirqb_routing" = "0x09" + register "pirqc_routing" = "0x0a" + register "pirqd_routing" = "0x09" + register "pirqe_routing" = "0x05" + register "pirqf_routing" = "0x80" + register "pirqg_routing" = "0x80" + register "pirqh_routing" = "0x0b" + device pci 1d.0 on end # USB UHCI Controller #1 device pci 1d.1 on end # USB UHCI Controller #2 device pci 1d.2 on end # USB UHCI Controller #3 Modified: trunk/coreboot-v2/src/mainboard/thomson/ip1000/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/thomson/ip1000/Config.lb 2009-05-08 00:19:13 UTC (rev 4258) +++ trunk/coreboot-v2/src/mainboard/thomson/ip1000/Config.lb 2009-05-08 00:24:24 UTC (rev 4259) @@ -80,6 +80,15 @@ register "rom_address" = "0xfff00000" end chip southbridge/intel/i82801xx # Southbridge + register "pirqa_routing" = "0x07" + register "pirqb_routing" = "0x09" + register "pirqc_routing" = "0x0a" + register "pirqd_routing" = "0x09" + register "pirqe_routing" = "0x05" + register "pirqf_routing" = "0x80" + register "pirqg_routing" = "0x80" + register "pirqh_routing" = "0x0b" + device pci 1d.0 on end # USB UHCI Controller #1 device pci 1d.1 on end # USB UHCI Controller #2 device pci 1d.2 on end # USB UHCI Controller #3 -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
