Author: hailfinger Date: 2009-05-09 04:30:21 +0200 (Sat, 09 May 2009) New Revision: 485
Modified: trunk/flash.h trunk/ichspi.c trunk/it87spi.c trunk/sb600spi.c trunk/spi.c trunk/wbsio_spi.c Log: Chips like the SST SST25VF080B can only handle single byte writes outside AAI mode. Change SPI architecture to handle 1-byte chunk chip writing differently from 256-byte chunk chip writing. Annotate SPI chip write functions with _256 or _1 suffix denoting the number of bytes they write at maximum. The 1-byte chunk writing is cut-n-pasted to different SPI drivers right now. A later patch can move them to the generic spi_chip_write_1. Signed-off-by: Carl-Daniel Hailfinger <[email protected]> Acked-by: Carl-Daniel Hailfinger <[email protected]> Modified: trunk/flash.h =================================================================== --- trunk/flash.h 2009-05-09 02:09:45 UTC (rev 484) +++ trunk/flash.h 2009-05-09 02:30:21 UTC (rev 485) @@ -617,6 +617,7 @@ int spi_chip_erase_d8(struct flashchip *flash); int spi_block_erase_52(const struct flashchip *flash, unsigned long addr); int spi_block_erase_d8(const struct flashchip *flash, unsigned long addr); +int spi_chip_write_1(struct flashchip *flash, uint8_t *buf); int spi_chip_write(struct flashchip *flash, uint8_t *buf); int spi_chip_read(struct flashchip *flash, uint8_t *buf); uint8_t spi_read_status_register(void); @@ -645,7 +646,7 @@ int ich_spi_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); int ich_spi_read(struct flashchip *flash, uint8_t * buf); -int ich_spi_write(struct flashchip *flash, uint8_t * buf); +int ich_spi_write_256(struct flashchip *flash, uint8_t * buf); /* it87spi.c */ extern uint16_t it8716f_flashport; @@ -653,13 +654,14 @@ int it8716f_spi_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); int it8716f_spi_chip_read(struct flashchip *flash, uint8_t *buf); -int it8716f_spi_chip_write(struct flashchip *flash, uint8_t *buf); +int it8716f_spi_chip_write_1(struct flashchip *flash, uint8_t *buf); +int it8716f_spi_chip_write_256(struct flashchip *flash, uint8_t *buf); /* sb600spi.c */ int sb600_spi_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); int sb600_spi_read(struct flashchip *flash, uint8_t *buf); -int sb600_spi_write(struct flashchip *flash, uint8_t *buf); +int sb600_spi_write_1(struct flashchip *flash, uint8_t *buf); uint8_t sb600_read_status_register(void); extern uint8_t volatile *sb600_spibar; @@ -758,7 +760,7 @@ int wbsio_check_for_spi(const char *name); int wbsio_spi_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); int wbsio_spi_read(struct flashchip *flash, uint8_t *buf); -int wbsio_spi_write(struct flashchip *flash, uint8_t *buf); +int wbsio_spi_write_1(struct flashchip *flash, uint8_t *buf); /* stm50flw0x0x.c */ int probe_stm50flw0x0x(struct flashchip *flash); Modified: trunk/ichspi.c =================================================================== --- trunk/ichspi.c 2009-05-09 02:09:45 UTC (rev 484) +++ trunk/ichspi.c 2009-05-09 02:30:21 UTC (rev 485) @@ -707,7 +707,7 @@ return rc; } -int ich_spi_write(struct flashchip *flash, uint8_t * buf) +int ich_spi_write_256(struct flashchip *flash, uint8_t * buf) { int i, j, rc = 0; int total_size = flash->total_size * 1024; Modified: trunk/it87spi.c =================================================================== --- trunk/it87spi.c 2009-05-09 02:09:45 UTC (rev 484) +++ trunk/it87spi.c 2009-05-09 02:30:21 UTC (rev 485) @@ -219,10 +219,12 @@ } /* - * IT8716F only allows maximum of 512 kb SPI mapped to LPC memory cycles * Program chip using firmware cycle byte programming. (SLOW!) + * This is for chips which can only handle one byte writes + * and for chips where memory mapped programming is impossible due to + * size constraints in IT87* (over 512 kB) */ -int it8716f_over512k_spi_chip_write(struct flashchip *flash, uint8_t *buf) +int it8716f_spi_chip_write_1(struct flashchip *flash, uint8_t *buf) { int total_size = 1024 * flash->total_size; int i; @@ -269,13 +271,17 @@ return 0; } -int it8716f_spi_chip_write(struct flashchip *flash, uint8_t *buf) +int it8716f_spi_chip_write_256(struct flashchip *flash, uint8_t *buf) { int total_size = 1024 * flash->total_size; int i; + /* + * IT8716F only allows maximum of 512 kb SPI chip size for memory + * mapped access. + */ if (total_size > 512 * 1024) { - it8716f_over512k_spi_chip_write(flash, buf); + it8716f_spi_chip_write_1(flash, buf); } else { for (i = 0; i < total_size / 256; i++) { it8716f_spi_page_program(i, buf, Modified: trunk/sb600spi.c =================================================================== --- trunk/sb600spi.c 2009-05-09 02:09:45 UTC (rev 484) +++ trunk/sb600spi.c 2009-05-09 02:30:21 UTC (rev 485) @@ -64,7 +64,7 @@ return readarr[0]; } -int sb600_spi_write(struct flashchip *flash, uint8_t *buf) +int sb600_spi_write_1(struct flashchip *flash, uint8_t *buf) { int rc = 0, i; int total_size = flash->total_size * 1024; Modified: trunk/spi.c =================================================================== --- trunk/spi.c 2009-05-09 02:09:45 UTC (rev 484) +++ trunk/spi.c 2009-05-09 02:30:21 UTC (rev 485) @@ -618,19 +618,45 @@ return 1; } +/* + * Program chip using byte programming. (SLOW!) + * This is for chips which can only handle one byte writes + * and for chips where memory mapped programming is impossible + * (e.g. due to size constraints in IT87* for over 512 kB) + */ +int spi_chip_write_1(struct flashchip *flash, uint8_t *buf) +{ + int total_size = 1024 * flash->total_size; + int i; + + spi_disable_blockprotect(); + for (i = 0; i < total_size; i++) { + spi_write_enable(); + spi_byte_program(i, buf[i]); + while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) + myusec_delay(10); + } + + return 0; +} + +/* + * Program chip using page (256 bytes) programming. + * Some SPI masters can't do this, they use single byte programming instead. + */ int spi_chip_write(struct flashchip *flash, uint8_t *buf) { switch (flashbus) { case BUS_TYPE_IT87XX_SPI: - return it8716f_spi_chip_write(flash, buf); + return it8716f_spi_chip_write_256(flash, buf); case BUS_TYPE_SB600_SPI: - return sb600_spi_write(flash, buf); + return sb600_spi_write_1(flash, buf); case BUS_TYPE_ICH7_SPI: case BUS_TYPE_ICH9_SPI: case BUS_TYPE_VIA_SPI: - return ich_spi_write(flash, buf); + return ich_spi_write_256(flash, buf); case BUS_TYPE_WBSIO_SPI: - return wbsio_spi_write(flash, buf); + return wbsio_spi_write_1(flash, buf); default: printf_debug ("%s called, but no SPI chipset/strapping detected\n", @@ -650,7 +676,7 @@ case BUS_TYPE_WBSIO_SPI: fprintf(stderr, "%s: impossible with Winbond SPI masters," " degrading to byte program\n", __func__); - return spi_chip_write(flash, buf); + return spi_chip_write_1(flash, buf); default: break; } Modified: trunk/wbsio_spi.c =================================================================== --- trunk/wbsio_spi.c 2009-05-09 02:09:45 UTC (rev 484) +++ trunk/wbsio_spi.c 2009-05-09 02:30:21 UTC (rev 485) @@ -186,7 +186,7 @@ return 0; } -int wbsio_spi_write(struct flashchip *flash, uint8_t *buf) +int wbsio_spi_write_1(struct flashchip *flash, uint8_t *buf) { int pos, size = flash->total_size * 1024; int result; -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
