Author: hailfinger Date: 2009-05-09 09:24:23 +0200 (Sat, 09 May 2009) New Revision: 487
Modified: trunk/ichspi.c Log: Trim default ICH SPI delay from 1000 to 10 microseconds. Since many commands take around 10 microseconds to complete, it is totally pointless to wait for 1000 microseconds before checking the status again. This patch is tested and reduced write time on ICH7 with SST25VF080B from over one hour to 62 seconds. Thanks to Ali Nadalizadeh for testing! Signed-off-by: Carl-Daniel Hailfinger <[email protected]> Acked-by: Myles Watson <[email protected]> Modified: trunk/ichspi.c =================================================================== --- trunk/ichspi.c 2009-05-09 02:34:18 UTC (rev 486) +++ trunk/ichspi.c 2009-05-09 07:24:23 UTC (rev 487) @@ -458,9 +458,9 @@ REGWRITE16(ICH7_REG_SPIC, temp16); /* wait for cycle complete */ - timeout = 1000 * 60; // 60s is a looong timeout. + timeout = 100 * 1000 * 60; // 60s is a looong timeout. while (((REGREAD16(ICH7_REG_SPIS) & SPIS_CDS) == 0) && --timeout) { - myusec_delay(1000); + myusec_delay(10); } if (!timeout) { printf_debug("timeout\n"); @@ -575,9 +575,9 @@ REGWRITE32(ICH9_REG_SSFS, temp32); /*wait for cycle complete */ - timeout = 1000 * 60; // 60s is a looong timeout. + timeout = 100 * 1000 * 60; // 60s is a looong timeout. while (((REGREAD32(ICH9_REG_SSFS) & SSFS_CDS) == 0) && --timeout) { - myusec_delay(1000); + myusec_delay(10); } if (!timeout) { printf_debug("timeout\n"); -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
