On 09.05.2009 05:42, Myles Watson wrote: > On Thu, May 7, 2009 at 6:45 PM, Carl-Daniel Hailfinger > <[email protected]> wrote: > >> Trim default ICH SPI delay from 1000 to 10 microseconds. Since many >> commands take around 10 microseconds to complete, it is totally >> pointless to wait for 1000 microseconds before checking the status again. >> >> This patch is tested and reduced write time on ICH7 with SST25VF080B >> from over one hour to 62 seconds. >> >> Thanks to Ali Nadalizadeh for testing! >> >> Signed-off-by: Carl-Daniel Hailfinger <[email protected]> >> > Acked-by: Myles Watson <[email protected]> > > I like the 1 hour to 62 seconds. >
Thanks, committed in r487. Regards, Carl-Daniel -- http://www.hailfinger.org/ -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
