[coreboot] Veriton FP2

[Quentin RAMEAU]

Hi,

I have got a Veriton FP2 ( http://www.acersupport.com/desktop/html/vfp2.html)
with a S511P motherboard, Intel 82815 northbridge and 82801BA southbridge.

I can do tests on it (socketed plcc32 bios and serial port available)
I attach informations from system to this mail, I can give more if needed.

/* This file was generated by getpir.c, do not modify!
 * (but if you do, please run checkpir on it to verify)
 *
 * Contains the IRQ Routing Table dumped directly from your
 * memory, which BIOS sets up.
 *
 * Documentation at: http://www.microsoft.com/whdc/archive/pciirq.mspx
 */

#ifdef GETPIR
#include "pirq_routing.h"
#else
#include <arch/pirq_routing.h>
#endif

const struct irq_routing_table intel_irq_routing_table = {
	PIRQ_SIGNATURE,  /* u32 signature */
	PIRQ_VERSION,    /* u16 version   */
	32+16*9,	 /* There can be total 9 devices on the bus */
	0x00,		 /* Where the interrupt router lies (bus) */
	(0x1f<<3)|0x0,   /* Where the interrupt router lies (dev) */
	0,		 /* IRQs devoted exclusively to PCI usage */
	0x8086,		 /* Vendor */
	0x2440,		 /* Device */
	0,		 /* Miniport */
	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
	0x20,		 /* u8 checksum. This has to be set to some
			    value that would give 0 after the sum of all
			    bytes for this structure (including checksum) */
	{
		/* bus,     dev|fn,   {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap},  slot, rfu */
		{0x00,(0x1f<<3)|0x0, {{0x00, 0xdef8}, {0x61, 0xdef8}, {0x6b, 0xdef8}, {0x63, 0xdef8}}, 0x0, 0x0},
		{0x00,(0x08<<3)|0x0, {{0x63, 0xdef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
		{0x00,(0x1e<<3)|0x0, {{0x60, 0xdef8}, {0x61, 0xdef8}, {0x62, 0xdef8}, {0x63, 0xdef8}}, 0x0, 0x0},
		{0x00,(0x01<<3)|0x0, {{0x60, 0xdef8}, {0x61, 0xdef8}, {0x62, 0xdef8}, {0x63, 0xdef8}}, 0x4, 0x0},
		{0x00,(0x02<<3)|0x0, {{0x60, 0xdef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
		{0x01,(0x00<<3)|0x0, {{0x60, 0xdef8}, {0x61, 0xdef8}, {0x62, 0xdef8}, {0x63, 0xdef8}}, 0x1, 0x0},
		{0x01,(0x08<<3)|0x0, {{0x68, 0xdef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x2, 0x0},
		{0xff,(0x00<<3)|0x2, {{0x41, 0x4643}, {0x47, 0x0201}, {0x06, 0x0000}, {0x00, 0x0119}}, 0x0, 0x0},
		{0x41,(0x1a<<3)|0x0, {{0x00, 0x5000}, {0x40, 0x0000}, {0x09, 0x0100}, {0x00, 0x8710}}, 0xf8, 0xc},
	}
};

unsigned long write_pirq_routing_table(unsigned long addr)
{
	return copy_pirq_routing_table(addr);
}

lspci
Description: Binary data

mptable
Description: Binary data

superiotool
Description: Binary data

-- 
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot