Author: myles Date: 2009-05-12 00:24:53 +0200 (Tue, 12 May 2009) New Revision: 4268
Modified: trunk/coreboot-v2/src/cpu/emulation/qemu-x86/northbridge.c trunk/coreboot-v2/src/devices/device.c trunk/coreboot-v2/src/devices/pci_device.c trunk/coreboot-v2/src/northbridge/intel/i440bx/northbridge.c Log: Trivial white space fixes so that the next patches are easier to read. Signed-off-by: Myles Watson <[email protected]> Acked-by: Myles Watson <[email protected]> Modified: trunk/coreboot-v2/src/cpu/emulation/qemu-x86/northbridge.c =================================================================== --- trunk/coreboot-v2/src/cpu/emulation/qemu-x86/northbridge.c 2009-05-11 13:45:11 UTC (rev 4267) +++ trunk/coreboot-v2/src/cpu/emulation/qemu-x86/northbridge.c 2009-05-11 22:24:53 UTC (rev 4268) @@ -83,16 +83,16 @@ for(rambits = 0, i = 0; i < ARRAY_SIZE(ramregs); i++) { unsigned char reg; reg = pci_read_config8(mc_dev, ramregs[i]); - /* these are ENDING addresses, not sizes. + /* these are ENDING addresses, not sizes. * if there is memory in this slot, then reg will be > rambits. - * So we just take the max, that gives us total. + * So we just take the max, that gives us total. * We take the highest one to cover for once and future coreboot * bugs. We warn about bugs. */ if (reg > rambits) rambits = reg; if (reg < rambits) - printk_err("ERROR! register 0x%x is not set!\n", + printk_err("ERROR! register 0x%x is not set!\n", ramregs[i]); } if (rambits == 0) { @@ -104,11 +104,11 @@ /* Compute the top of Low memory */ tolmk = pci_tolm >> 10; if (tolmk >= tomk) { - /* The PCI hole does not overlap memory. - */ + /* The PCI hole does not overlap the memory. */ tolmk = tomk; } - /* Report the memory regions */ + + /* Report the memory regions. */ idx = 10; ram_resource(dev, idx++, 0, tolmk); } @@ -122,12 +122,12 @@ } static struct device_operations pci_domain_ops = { - .read_resources = pci_domain_read_resources, - .set_resources = pci_domain_set_resources, - .enable_resources = enable_childrens_resources, - .init = 0, - .scan_bus = pci_domain_scan_bus, -}; + .read_resources = pci_domain_read_resources, + .set_resources = pci_domain_set_resources, + .enable_resources = enable_childrens_resources, + .init = 0, + .scan_bus = pci_domain_scan_bus, +}; static void enable_dev(struct device *dev) { Modified: trunk/coreboot-v2/src/devices/device.c =================================================================== --- trunk/coreboot-v2/src/devices/device.c 2009-05-11 13:45:11 UTC (rev 4267) +++ trunk/coreboot-v2/src/devices/device.c 2009-05-11 22:24:53 UTC (rev 4268) @@ -17,10 +17,10 @@ /* * (c) 1999--2000 Martin Mares <[email protected]> */ -/* lots of mods by ron minnich ([email protected]), with +/* lots of mods by ron minnich ([email protected]), with * the final architecture guidance from Tom Merritt ([email protected]) - * In particular, we changed from the one-pass original version to - * Tom's recommended multiple-pass version. I wasn't sure about doing + * In particular, we changed from the one-pass original version to + * Tom's recommended multiple-pass version. I wasn't sure about doing * it with multiple passes, until I actually started doing it and saw * the wisdom of Tom's recommendations ... * @@ -52,7 +52,7 @@ /** * @brief Allocate a new device structure. - * + * * Allocte a new device structure and attached it to the device tree as a * child of the parent bus. * @@ -69,7 +69,7 @@ device_t dev, child; int link; - spin_lock(&dev_lock); + spin_lock(&dev_lock); /* Find the last child of our parent */ for(child = parent->children; child && child->sibling; ) { @@ -111,7 +111,7 @@ } /** - * @brief round a number up to an alignment. + * @brief round a number up to an alignment. * @param val the starting value * @param roundup Alignment as a power of two * @returns rounded up number @@ -158,7 +158,7 @@ struct resource *resource; unsigned link; resource = &curdev->resource[i]; - if (!(resource->flags & IORESOURCE_SUBTRACTIVE)) + if (!(resource->flags & IORESOURCE_SUBTRACTIVE)) continue; link = IOINDEX_SUBTRACTIVE_LINK(resource->index); if (link > MAX_LINKS) { @@ -194,24 +194,23 @@ state->seen_last = 1; return; } - if (resource->flags & IORESOURCE_FIXED ) return; //skip it - if (last && ( - (last->align < resource->align) || - ((last->align == resource->align) && - (last->size < resource->size)) || - ((last->align == resource->align) && - (last->size == resource->size) && - (!state->seen_last)))) { + if (resource->flags & IORESOURCE_FIXED) + return; // Skip it. + if (last && ((last->align < resource->align) || + ((last->align == resource->align) && + (last->size < resource->size)) || + ((last->align == resource->align) && + (last->size == resource->size) && (!state->seen_last)))) { return; } - if (!state->result || - (state->result->align < resource->align) || - ((state->result->align == resource->align) && - (state->result->size < resource->size))) + if (!state->result || + (state->result->align < resource->align) || + ((state->result->align == resource->align) && + (state->result->size < resource->size))) { state->result_dev = dev; state->result = resource; - } + } } static struct device *largest_resource(struct bus *bus, struct resource **result_res, @@ -224,14 +223,15 @@ state.result = 0; state.seen_last = 0; - search_bus_resources(bus, type_mask, type, pick_largest_resource, &state); + search_bus_resources(bus, type_mask, type, pick_largest_resource, + &state); *result_res = state.result; return state.result_dev; } /* Compute allocate resources is the guts of the resource allocator. - * + * * The problem. * - Allocate resources locations for every device. * - Don't overlap, and follow the rules of bridges. @@ -253,7 +253,7 @@ * bridges. The first to see how large the resources are behind * the bridge, and what their alignment requirements are. The * second to assign a safe address to the devices behind the - * bridge. This allows me to treat a bridge as just a device with + * bridge. This allows me to treat a bridge as just a device with * a couple of resources, and not need to special case it in the * allocator. Also this allows handling of other types of bridges. * @@ -272,7 +272,7 @@ min_align = 0; base = bridge->base; - printk_spew("%s compute_allocate_resource %s: base: %08Lx size: %08Lx align: %d gran: %d\n", + printk_spew("%s compute_allocate_resource %s: base: %08Lx size: %08Lx align: %d gran: %d\n", dev_path(bus->dev), (bridge->flags & IORESOURCE_IO)? "io": (bridge->flags & IORESOURCE_PREFETCH)? "prefmem" : "mem", @@ -295,7 +295,7 @@ /* Remember I haven't found anything yet. */ resource = 0; - /* Walk through all the devices on the current bus and + /* Walk through all the devices on the current bus and * compute the addresses. */ while((dev = largest_resource(bus, &resource, type_mask, type))) { @@ -356,11 +356,11 @@ resource->flags |= IORESOURCE_ASSIGNED; resource->flags &= ~IORESOURCE_STORED; base += size; - + printk_spew("%s %02lx * [0x%08Lx - 0x%08Lx] %s\n", dev_path(dev), - resource->index, - resource->base, + resource->index, + resource->base, resource->base + resource->size - 1, (resource->flags & IORESOURCE_IO)? "io": (resource->flags & IORESOURCE_PREFETCH)? "prefmem": "mem"); @@ -380,13 +380,11 @@ */ bridge->size = round(base, bridge->gran) - bridge->base; - printk_spew("%s compute_allocate_resource %s: base: %08Lx size: %08Lx align: %d gran: %d done\n", - dev_path(bus->dev), - (bridge->flags & IORESOURCE_IO)? "io": - (bridge->flags & IORESOURCE_PREFETCH)? "prefmem" : "mem", - base, bridge->size, bridge->align, bridge->gran); - - + printk_spew("%s compute_allocate_resource %s: base: %08Lx size: %08Lx align: %d gran: %d done\n", + dev_path(bus->dev), + (bridge->flags & IORESOURCE_IO)? "io": + (bridge->flags & IORESOURCE_PREFETCH)? "prefmem" : "mem", + base, bridge->size, bridge->align, bridge->gran); } #if CONFIG_CONSOLE_VGA == 1 @@ -407,7 +405,7 @@ for(dev = all_devices; dev; dev = dev->next) { if (!dev->enabled) continue; if (((dev->class >> 16) == PCI_BASE_CLASS_DISPLAY) && - ((dev->class >> 8) != PCI_CLASS_DISPLAY_OTHER)) + ((dev->class >> 8) != PCI_CLASS_DISPLAY_OTHER)) { if (!vga_first) { if (dev->on_mainboard) { @@ -427,7 +425,7 @@ dev->command &= ~(PCI_COMMAND_MEMORY | PCI_COMMAND_IO); } } - + vga = vga_last; if(!vga) { @@ -443,7 +441,7 @@ vga = vga_onboard; } - + if (vga) { /* vga is first add on card or the only onboard vga */ printk_debug("Allocating VGA resource %s\n", dev_path(vga)); @@ -458,7 +456,7 @@ dev_path(bus->dev)); bus->bridge_ctrl |= PCI_BRIDGE_CTL_VGA; bus = (bus == bus->dev->bus)? 0 : bus->dev->bus; - } + } } #endif @@ -481,7 +479,7 @@ { struct device *curdev; - printk_spew("%s assign_resources, bus %d link: %d\n", + printk_spew("%s assign_resources, bus %d link: %d\n", dev_path(bus->dev), bus->secondary, bus->link); for(curdev = bus->children; curdev; curdev = curdev->sibling) { @@ -495,7 +493,7 @@ } curdev->ops->set_resources(curdev); } - printk_spew("%s assign_resources, bus %d link: %d\n", + printk_spew("%s assign_resources, bus %d link: %d\n", dev_path(bus->dev), bus->secondary, bus->link); } @@ -529,7 +527,7 @@ dev->ops->enable_resources(dev); } -/** +/** * @brief Reset all of the devices a bus * * Reset all of the devices on a bus and clear the bus's reset_needed flag. @@ -550,11 +548,11 @@ return 0; } -/** +/** * @brief Scan for devices on a bus. * * If there are bridges on the bus, recursively scan the buses behind the bridges. - * If the setting up and tuning of the bus causes a reset to be required, + * If the setting up and tuning of the bus causes a reset to be required, * reset the bus and scan it again. * * @param bus pointer to the bus device @@ -612,7 +610,7 @@ * This function has no idea how to scan and probe buses and devices at all. * It depends on the bus/device specific scan_bus() method to do it. The * scan_bus() method also has to create the device structure and attach - * it to the device tree. + * it to the device tree. */ void dev_enumerate(void) { @@ -633,7 +631,7 @@ /** * @brief Configure devices on the devices tree. - * + * * Starting at the root of the device tree, travel it recursively in two * passes. In the first pass, we compute and allocate resources (ranges) * requried by each device. In the second pass, the resources ranges are @@ -643,7 +641,7 @@ * at DEVICE_MEM_HIGH and grow downward. * * Since the assignment is hierarchical we set the values into the dev_root - * struct. + * struct. */ void dev_configure(void) { @@ -682,7 +680,7 @@ #if CONFIG_CONSOLE_VGA == 1 /* Allocate the VGA I/O resource.. */ - allocate_vga_resource(); + allocate_vga_resource(); #endif /* Store the computed resource allocations into device registers ... */ @@ -726,8 +724,8 @@ printk_info("Initializing devices...\n"); for(dev = all_devices; dev; dev = dev->next) { - if (dev->enabled && !dev->initialized && - dev->ops && dev->ops->init) + if (dev->enabled && !dev->initialized && + dev->ops && dev->ops->init) { if (dev->path.type == DEVICE_PATH_I2C) { printk_debug("smbus: %s[%d]->", Modified: trunk/coreboot-v2/src/devices/pci_device.c =================================================================== --- trunk/coreboot-v2/src/devices/pci_device.c 2009-05-11 13:45:11 UTC (rev 4267) +++ trunk/coreboot-v2/src/devices/pci_device.c 2009-05-11 22:24:53 UTC (rev 4268) @@ -55,7 +55,7 @@ { uint8_t value, ones, zeroes; value = pci_read_config8(dev, reg); - + pci_write_config8(dev, reg, 0xff); ones = pci_read_config8(dev, reg); @@ -71,7 +71,7 @@ { uint16_t value, ones, zeroes; value = pci_read_config16(dev, reg); - + pci_write_config16(dev, reg, 0xffff); ones = pci_read_config16(dev, reg); @@ -87,7 +87,7 @@ { uint32_t value, ones, zeroes; value = pci_read_config32(dev, reg); - + pci_write_config32(dev, reg, 0xffffffff); ones = pci_read_config32(dev, reg); @@ -146,7 +146,7 @@ } -/** Given a device and register, read the size of the BAR for that register. +/** Given a device and register, read the size of the BAR for that register. * @param dev Pointer to the device structure * @param resource Pointer to the resource structure * @param index Address of the pci configuration register @@ -176,7 +176,7 @@ /* Find the high bits that move */ moving |= ((resource_t)pci_moving_config32(dev, index + 4)) << 32; } - /* Find the resource constraints. + /* Find the resource constraints. * * Start by finding the bits that move. From there: * - Size is the least significant bit of the bits that move. @@ -195,12 +195,12 @@ resource->limit = limit = moving | (resource->size - 1); } /* - * some broken hardware has read-only registers that do not + * some broken hardware has read-only registers that do not * really size correctly. - * Example: the acer m7229 has BARs 1-4 normally read-only. + * Example: the acer m7229 has BARs 1-4 normally read-only. * so BAR1 at offset 0x10 reads 0x1f1. If you size that register - * by writing 0xffffffff to it, it will read back as 0x1f1 -- a - * violation of the spec. + * by writing 0xffffffff to it, it will read back as 0x1f1 -- a + * violation of the spec. * We catch this case and ignore it by observing which bits move, * This also catches the common case unimplemented registers * that always read back as 0. @@ -219,7 +219,7 @@ resource->flags |= IORESOURCE_IO; /* I don't want to deal with 32bit I/O resources */ resource->limit = 0xffff; - } + } else { /* A Memory mapped base address */ attr &= PCI_BASE_ADDRESS_MEM_ATTR_MASK; @@ -290,7 +290,7 @@ /* clear the Enable bit */ moving = moving & ~PCI_ROM_ADDRESS_ENABLE; - /* Find the resource constraints. + /* Find the resource constraints. * * Start by finding the bits that move. From there: * - Size is the least significant bit of the bits that move. @@ -325,12 +325,12 @@ resource->base = dev->rom_address; resource->flags |= IORESOURCE_MEM | IORESOURCE_READONLY | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - } + } compact_resources(dev); } -/** Read the base address registers for a given device. +/** Read the base address registers for a given device. * @param dev Pointer to the dev structure * @param howmany How many registers to read (6 for device, 2 for bridge) */ @@ -405,7 +405,7 @@ /* Initialize the io space constraints on the current bus */ pci_record_bridge_resource( - dev, moving, PCI_IO_BASE, + dev, moving, PCI_IO_BASE, IORESOURCE_IO, IORESOURCE_IO); @@ -415,15 +415,15 @@ moving_limit = ((resource_t)pci_moving_config16(dev, PCI_PREF_MEMORY_LIMIT)) << 16; moving_limit |= ((resource_t)pci_moving_config32(dev, PCI_PREF_LIMIT_UPPER32)) << 32; - + moving = moving_base & moving_limit; /* Initiliaze the prefetchable memory constraints on the current bus */ pci_record_bridge_resource( - dev, moving, PCI_PREF_MEMORY_BASE, + dev, moving, PCI_PREF_MEMORY_BASE, IORESOURCE_MEM | IORESOURCE_PREFETCH, IORESOURCE_MEM | IORESOURCE_PREFETCH); - + /* See if the bridge mem resources are implemented */ moving_base = ((uint32_t)pci_moving_config16(dev, PCI_MEMORY_BASE)) << 16; moving_limit = ((uint32_t)pci_moving_config16(dev, PCI_MEMORY_LIMIT)) << 16; @@ -432,7 +432,7 @@ /* Initialize the memory resources on the current bus */ pci_record_bridge_resource( - dev, moving, PCI_MEMORY_BASE, + dev, moving, PCI_MEMORY_BASE, IORESOURCE_MEM | IORESOURCE_PREFETCH, IORESOURCE_MEM); @@ -496,13 +496,13 @@ /* Get the end */ end = resource_end(resource); - + /* Now store the resource */ resource->flags |= IORESOURCE_STORED; if (!(resource->flags & IORESOURCE_PCI_BRIDGE)) { unsigned long base_lo, base_hi; /* - * some chipsets allow us to set/clear the IO bit. + * some chipsets allow us to set/clear the IO bit. * (e.g. VIA 82c686a.) So set it to be safe) */ base_lo = base & 0xffffffff; @@ -517,7 +517,7 @@ } else if (resource->index == PCI_IO_BASE) { /* set the IO ranges */ - compute_allocate_resource(&dev->link[0], resource, + compute_allocate_resource(&dev->link[0], resource, IORESOURCE_IO, IORESOURCE_IO); pci_write_config8(dev, PCI_IO_BASE, base >> 8); pci_write_config16(dev, PCI_IO_BASE_UPPER16, base >> 16); @@ -527,7 +527,7 @@ else if (resource->index == PCI_MEMORY_BASE) { /* set the memory range */ compute_allocate_resource(&dev->link[0], resource, - IORESOURCE_MEM | IORESOURCE_PREFETCH, + IORESOURCE_MEM | IORESOURCE_PREFETCH, IORESOURCE_MEM); pci_write_config16(dev, PCI_MEMORY_BASE, base >> 16); pci_write_config16(dev, PCI_MEMORY_LIMIT, end >> 16); @@ -535,7 +535,7 @@ else if (resource->index == PCI_PREF_MEMORY_BASE) { /* set the prefetchable memory range */ compute_allocate_resource(&dev->link[0], resource, - IORESOURCE_MEM | IORESOURCE_PREFETCH, + IORESOURCE_MEM | IORESOURCE_PREFETCH, IORESOURCE_MEM | IORESOURCE_PREFETCH); pci_write_config16(dev, PCI_PREF_MEMORY_BASE, base >> 16); pci_write_config32(dev, PCI_PREF_BASE_UPPER32, base >> 32); @@ -597,10 +597,10 @@ ops = ops_pci(dev); if (dev->on_mainboard && ops && ops->set_subsystem) { printk_debug("%s subsystem <- %02x/%02x\n", - dev_path(dev), + dev_path(dev), MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID, MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID); - ops->set_subsystem(dev, + ops->set_subsystem(dev, MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID, MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID); } @@ -642,7 +642,7 @@ void pci_dev_set_subsystem(device_t dev, unsigned vendor, unsigned device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, ((device & 0xffff) << 16) | (vendor & 0xffff)); } @@ -722,12 +722,12 @@ * to figure out the type of downstream bridge. PCI-X * PCI-E, and Hypertransport all seem to have appropriate * capabilities. - * + * * When only a PCI-Express capability is found the type * is examined to see which type of bridge we have. * * @param dev - * + * * @return appropriate bridge operations */ static struct device_operations *get_pci_bridge_ops(device_t dev) @@ -751,7 +751,7 @@ flags = pci_read_config16(dev, pos + PCI_CAP_FLAGS); if ((flags >> 13) == 1) { /* Host or Secondary Interface */ - printk_debug("%s subbordinate bus Hypertransport\n", + printk_debug("%s subbordinate bus Hypertransport\n", dev_path(dev)); return &default_ht_ops_bus; } @@ -766,11 +766,11 @@ case PCI_EXP_TYPE_ROOT_PORT: case PCI_EXP_TYPE_UPSTREAM: case PCI_EXP_TYPE_DOWNSTREAM: - printk_debug("%s subbordinate bus PCI Express\n", + printk_debug("%s subbordinate bus PCI Express\n", dev_path(dev)); return &default_pciexp_ops_bus; case PCI_EXP_TYPE_PCI_BRIDGE: - printk_debug("%s subbordinate PCI\n", + printk_debug("%s subbordinate PCI\n", dev_path(dev)); return &default_pci_ops_bus; default: @@ -785,7 +785,7 @@ * @brief Set up PCI device operation * * - * @param dev + * @param dev * * @see pci_drivers */ @@ -797,14 +797,14 @@ } /* Look through the list of setup drivers and find one for - * this pci device + * this pci device */ for(driver = &pci_drivers[0]; driver != &epci_drivers[0]; driver++) { if ((driver->vendor == dev->vendor) && - (driver->device == dev->device)) + (driver->device == dev->device)) { dev->ops = driver->ops; - printk_spew("%s [%04x/%04x] %sops\n", + printk_spew("%s [%04x/%04x] %sops\n", dev_path(dev), driver->vendor, driver->device, (driver->ops->scan_bus?"bus ":"")); @@ -835,7 +835,7 @@ printk_err("%s [%04x/%04x/%06x] has unknown header " "type %02x, ignoring.\n", dev_path(dev), - dev->vendor, dev->device, + dev->vendor, dev->device, dev->class >> 8, dev->hdr_type); } } @@ -875,9 +875,9 @@ break; } } - /* Just like alloc_dev add the device to the list of device on the bus. - * When the list of devices was formed we removed all of the parents - * children, and now we are interleaving static and dynamic devices in + /* Just like alloc_dev add the device to the list of device on the bus. + * When the list of devices was formed we removed all of the parents + * children, and now we are interleaving static and dynamic devices in * order on the bus. */ if (dev) { @@ -897,7 +897,7 @@ return dev; } -/** +/** * @brief Scan a PCI bus. * * Determine the existence of a given PCI device. @@ -936,13 +936,13 @@ * found the device specific operations this * operations we will disable the device with * those as well. - * + * * This is geared toward devices that have subfunctions * that do not show up by default. - * + * * If a device is a stuff option on the motherboard * it may be absent and enable_dev must cope. - * + * */ /* Run the magice enable sequence for the device */ if (dev->chip_ops && dev->chip_ops->enable_dev) { @@ -950,8 +950,8 @@ } /* Now read the vendor and device id */ id = pci_read_config32(dev, PCI_VENDOR_ID); - - + + /* If the device does not have a pci id disable it. * Possibly this is because we have already disabled * the device. But this also handles optional devices @@ -959,7 +959,7 @@ */ /* If the chain is fully enumerated quit */ if ( (id == 0xffffffff) || (id == 0x00000000) || - (id == 0x0000ffff) || (id == 0xffff0000)) + (id == 0x0000ffff) || (id == 0xffff0000)) { if (dev->enabled) { printk_info("Disabling static device: %s\n", @@ -972,22 +972,22 @@ /* Read the rest of the pci configuration information */ hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE); class = pci_read_config32(dev, PCI_CLASS_REVISION); - + /* Store the interesting information in the device structure */ dev->vendor = id & 0xffff; dev->device = (id >> 16) & 0xffff; dev->hdr_type = hdr_type; /* class code, the upper 3 bytes of PCI_CLASS_REVISION */ dev->class = class >> 8; - + /* Architectural/System devices always need to * be bus masters. */ if ((dev->class >> 16) == PCI_BASE_CLASS_SYSTEM) { dev->command |= PCI_COMMAND_MASTER; } - /* Look at the vendor and device id, or at least the + /* Look at the vendor and device id, or at least the * header type and class and figure out which set of * configuration methods to use. Unless we already * have some pci ops. @@ -998,14 +998,14 @@ if (dev->ops && dev->ops->enable) { dev->ops->enable(dev); } - + /* Display the device and error if we don't have some pci operations * for it. */ printk_debug("%s [%04x/%04x] %s%s\n", dev_path(dev), - dev->vendor, dev->device, + dev->vendor, dev->device, dev->enabled?"enabled": "disabled", dev->ops?"" : " No operations" ); @@ -1013,7 +1013,7 @@ return dev; } -/** +/** * @brief Scan a PCI bus. * * Determine the existence of devices and bridges on a PCI bus. If there are @@ -1059,14 +1059,14 @@ /* See if a device is present and setup the device * structure. */ - dev = pci_probe_dev(dev, bus, devfn); + dev = pci_probe_dev(dev, bus, devfn); - /* if this is not a multi function device, + /* if this is not a multi function device, * or the device is not present don't waste - * time probing another function. - * Skip to next device. + * time probing another function. + * Skip to next device. */ - if ((PCI_FUNC(devfn) == 0x00) && + if ((PCI_FUNC(devfn) == 0x00) && (!dev || (dev->enabled && ((dev->hdr_type & 0x80) != 0x80)))) { devfn += 0x07; @@ -1074,7 +1074,7 @@ } post_code(0x25); - /* Die if any left over static devices are are found. + /* Die if any left over static devices are are found. * There's probably a problem in the Config.lb. */ if(old_devices) { @@ -1118,8 +1118,8 @@ * * @return The maximum bus number found, after scanning all subordinate busses */ -unsigned int do_pci_scan_bridge(struct device *dev, unsigned int max, - unsigned int (*do_scan_bus)(struct bus *bus, +unsigned int do_pci_scan_bridge(struct device *dev, unsigned int max, + unsigned int (*do_scan_bus)(struct bus *bus, unsigned min_devfn, unsigned max_devfn, unsigned int max)) { struct bus *bus; @@ -1134,7 +1134,7 @@ /* Set up the primary, secondary and subordinate bus numbers. We have * no idea how many buses are behind this bridge yet, so we set the - * subordinate bus number to 0xff for the moment. + * subordinate bus number to 0xff for the moment. */ bus->secondary = ++max; bus->subordinate = 0xff; @@ -1160,7 +1160,7 @@ ((unsigned int) (bus->subordinate) << 16)); pci_write_config32(dev, PCI_PRIMARY_BUS, buses); - /* Now we can scan all subordinate buses + /* Now we can scan all subordinate buses * i.e. the bus behind the bridge. */ max = do_scan_bus(bus, 0x00, 0xff, max); @@ -1173,7 +1173,7 @@ ((unsigned int) (bus->subordinate) << 16); pci_write_config32(dev, PCI_PRIMARY_BUS, buses); pci_write_config16(dev, PCI_COMMAND, cr); - + printk_spew("%s returns max %d\n", __func__, max); return max; } @@ -1231,10 +1231,10 @@ the indicated device address. If the device does not exist or does not require interrupts then this function has no effect. - This function should be called for each PCI slot in your system. + This function should be called for each PCI slot in your system. pIntAtoD is an array of IRQ #s that are assigned to PINTA through PINTD of - this slot. + this slot. The particular irq #s that are passed in depend on the routing inside your southbridge and on your motherboard. @@ -1256,7 +1256,7 @@ if (pdev) { line = pci_read_config8(pdev, PCI_INTERRUPT_PIN); - // PCI spec says all other values are reserved + // PCI spec says all other values are reserved if ((line >= 1) && (line <= 4)) { irq = pIntAtoD[line - 1]; Modified: trunk/coreboot-v2/src/northbridge/intel/i440bx/northbridge.c =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/i440bx/northbridge.c 2009-05-11 13:45:11 UTC (rev 4267) +++ trunk/coreboot-v2/src/northbridge/intel/i440bx/northbridge.c 2009-05-11 22:24:53 UTC (rev 4268) @@ -13,7 +13,7 @@ #include "northbridge.h" #include "i440bx.h" -static void northbridge_init(device_t dev) +static void northbridge_init(device_t dev) { printk_spew("Northbridge Init\n"); } @@ -30,7 +30,7 @@ static const struct pci_driver northbridge_driver __pci_driver = { .ops = &northbridge_operations, .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x7190, + .device = 0x7190, }; @@ -38,33 +38,32 @@ static void pci_domain_read_resources(device_t dev) { - struct resource *resource; - unsigned reg; + struct resource *resource; - /* Initialize the system wide io space constraints */ - resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); - resource->limit = 0xffffUL; - resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; + /* Initialize the system wide io space constraints */ + resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0)); + resource->limit = 0xffffUL; + resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; - /* Initialize the system wide memory resources constraints */ - resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); - resource->limit = 0xffffffffULL; - resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; + /* Initialize the system wide memory resources constraints */ + resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0)); + resource->limit = 0xffffffffULL; + resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; } static void ram_resource(device_t dev, unsigned long index, - unsigned long basek, unsigned long sizek) + unsigned long basek, unsigned long sizek) { - struct resource *resource; + struct resource *resource; - if (!sizek) { - return; - } - resource = new_resource(dev, index); - resource->base = ((resource_t)basek) << 10; - resource->size = ((resource_t)sizek) << 10; - resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | \ - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; + if (!sizek) { + return; + } + resource = new_resource(dev, index); + resource->base = ((resource_t)basek) << 10; + resource->size = ((resource_t)sizek) << 10; + resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | \ + IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; } static void tolm_test(void *gp, struct device *dev, struct resource *new) @@ -95,6 +94,7 @@ #define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB extern uint64_t high_tables_base, high_tables_size; #endif + static void pci_domain_set_resources(device_t dev) { device_t mc_dev; @@ -102,7 +102,6 @@ pci_tolm = find_pci_tolm(&dev->link[0]); mc_dev = dev->link[0].children; - if (mc_dev) { uint16_t tolm_r; unsigned long tomk, tolmk; @@ -123,7 +122,7 @@ tolmk = pci_tolm / 1024; if (tolmk >= tomk) { - /* The PCI hole does does not overlap the memory. */ + /* The PCI hole does not overlap the memory. */ tolmk = tomk; } @@ -131,34 +130,33 @@ idx = 10; ram_resource(dev, idx++, 0, 640); ram_resource(dev, idx++, 768, tolmk - 768); - + #if HAVE_HIGH_TABLES==1 /* Leave some space for ACPI, PIRQ and MP tables */ high_tables_base = (tomk - HIGH_TABLES_SIZE) * 1024; high_tables_size = HIGH_TABLES_SIZE * 1024; #endif } - assign_resources(&dev->link[0]); } static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max) { - max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max); - return max; + max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max); + return max; } static struct device_operations pci_domain_ops = { - .read_resources = pci_domain_read_resources, - .set_resources = pci_domain_set_resources, - .enable_resources = enable_childrens_resources, - .init = 0, - .scan_bus = pci_domain_scan_bus, -}; + .read_resources = pci_domain_read_resources, + .set_resources = pci_domain_set_resources, + .enable_resources = enable_childrens_resources, + .init = 0, + .scan_bus = pci_domain_scan_bus, +}; static void cpu_bus_init(device_t dev) { - initialize_cpus(&dev->link[0]); + initialize_cpus(&dev->link[0]); } static void cpu_bus_noop(device_t dev) @@ -166,25 +164,23 @@ } static struct device_operations cpu_bus_ops = { - .read_resources = cpu_bus_noop, - .set_resources = cpu_bus_noop, - .enable_resources = cpu_bus_noop, - .init = cpu_bus_init, - .scan_bus = 0, + .read_resources = cpu_bus_noop, + .set_resources = cpu_bus_noop, + .enable_resources = cpu_bus_noop, + .init = cpu_bus_init, + .scan_bus = 0, }; static void enable_dev(struct device *dev) { - struct device_path path; - - /* Set the operations if it is a special bus type */ - if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) { - dev->ops = &pci_domain_ops; + /* Set the operations if it is a special bus type */ + if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) { + dev->ops = &pci_domain_ops; pci_set_method(dev); - } - else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) { - dev->ops = &cpu_bus_ops; - } + } + else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) { + dev->ops = &cpu_bus_ops; + } } struct chip_operations northbridge_intel_i440bx_ops = { -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
