Author: hailfinger Date: 2009-05-14 00:19:12 +0200 (Thu, 14 May 2009) New Revision: 504
Modified: trunk/flashchips.c Log: SST25 chips do not support page program, only byte program. Downgrade the chips from 256-byte writes to 1-byte writes. This fixes writing to them on ICH/VIA SPI masters. Signed-off-by: Carl-Daniel Hailfinger <[email protected]> Acked-by: FENG Yu Ning <[email protected]> Modified: trunk/flashchips.c =================================================================== --- trunk/flashchips.c 2009-05-13 22:18:35 UTC (rev 503) +++ trunk/flashchips.c 2009-05-13 22:19:12 UTC (rev 504) @@ -1182,7 +1182,7 @@ .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .erase = spi_chip_erase_c7, - .write = spi_chip_write_256, + .write = spi_chip_write_1, .read = spi_chip_read, }, @@ -1196,7 +1196,7 @@ .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .erase = spi_chip_erase_c7, - .write = spi_chip_write_256, + .write = spi_chip_write_1, .read = spi_chip_read, }, @@ -1210,7 +1210,7 @@ .tested = TEST_UNTESTED, .probe = probe_spi_rdid, .erase = spi_chip_erase_c7, - .write = spi_chip_write_256, + .write = spi_chip_write_1, .read = spi_chip_read, }, @@ -1224,7 +1224,7 @@ .tested = TEST_OK_PR, .probe = probe_spi_rems, .erase = spi_chip_erase_60, - .write = spi_chip_write_256, + .write = spi_chip_write_1, .read = spi_chip_read, }, @@ -1238,7 +1238,7 @@ .tested = TEST_OK_PR, .probe = probe_spi_rems, .erase = spi_chip_erase_c7, - .write = spi_aai_write, + .write = spi_chip_write_1, .read = spi_chip_read, }, -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
