Carl-Daniel Hailfinger wrote: > The docs are not yet public, so I don't know.
The question was for someone else who knows. > > I guess you're using the SPI BAR value as part of the heuristic. > > Since accessing the SPI master is completely impossible if the SPI > BAR is located at 0x0 Sure, but a valid BAR does not a flash chip present make. > OTOH, even if no SPI chip is attached, probing will not hang as > long as the BAR is not at 0x0. Do you know what will actually happen in that case? //Peter -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
