On Wed, 27 May 2009 00:06:57 -0400, Joseph Smith <[email protected]>
wrote:
> Sorry so late, here is the patch to enable/disable IDE 0/1
> (Primary/Secondary) interfaces on the i82801xx southbridge.
>
Oops, helps if the patch is attached.
--
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org
Index: src/southbridge/intel/i82801xx/chip.h
===================================================================
--- src/southbridge/intel/i82801xx/chip.h (revision 4311)
+++ src/southbridge/intel/i82801xx/chip.h (working copy)
@@ -43,6 +43,8 @@
uint8_t pirqf_routing;
uint8_t pirqg_routing;
uint8_t pirqh_routing;
+ uint8_t ide0_enable;
+ uint8_t ide1_enable;
};
extern struct chip_operations southbridge_intel_i82801xx_ops;
Index: src/southbridge/intel/i82801xx/i82801xx_ide.c
===================================================================
--- src/southbridge/intel/i82801xx/i82801xx_ide.c (revision 4311)
+++ src/southbridge/intel/i82801xx/i82801xx_ide.c (working copy)
@@ -27,29 +27,36 @@
#include <device/pci_ids.h>
#include "i82801xx.h"
+typedef struct southbridge_intel_i82801xx_config config_t;
+
static void ide_init(struct device *dev)
{
+ /* Get the chip configuration */
+ config_t *config = dev->chip_info;
+
/* TODO: Needs to be tested for compatibility with ICH5(R). */
/* Enable IDE devices so the Linux IDE driver will work. */
uint16_t ideTimingConfig;
- int enable_primary = 1;
- int enable_secondary = 1;
ideTimingConfig = pci_read_config16(dev, IDE_TIM_PRI);
ideTimingConfig &= ~IDE_DECODE_ENABLE;
- if (enable_primary) {
+ if (config->ide0_enable) {
/* Enable primary IDE interface. */
ideTimingConfig |= IDE_DECODE_ENABLE;
- printk_debug("IDE0 ");
+ printk_debug("IDE0: Primary IDE interface is enabled\n");
+ } else {
+ printk_info("IDE0: Primary IDE interface is disabled\n");
}
pci_write_config16(dev, IDE_TIM_PRI, ideTimingConfig);
ideTimingConfig = pci_read_config16(dev, IDE_TIM_SEC);
ideTimingConfig &= ~IDE_DECODE_ENABLE;
- if (enable_secondary) {
+ if (config->ide1_enable) {
/* Enable secondary IDE interface. */
ideTimingConfig |= IDE_DECODE_ENABLE;
- printk_debug("IDE1 ");
+ printk_debug("IDE1: Secondary IDE interface is enabled\n");
+ } else {
+ printk_info("IDE1: Secondary IDE interface is disabled\n");
}
pci_write_config16(dev, IDE_TIM_SEC, ideTimingConfig);
}
Index: src/mainboard/thomson/ip1000/Config.lb
===================================================================
--- src/mainboard/thomson/ip1000/Config.lb (revision 4311)
+++ src/mainboard/thomson/ip1000/Config.lb (working copy)
@@ -89,6 +89,9 @@
register "pirqg_routing" = "0x80"
register "pirqh_routing" = "0x0b"
+ register "ide0_enable" = "1"
+ register "ide1_enable" = "1"
+
device pci 1d.0 on end # USB UHCI Controller #1
device pci 1d.1 on end # USB UHCI Controller #2
device pci 1d.2 on end # USB UHCI Controller #3
Index: src/mainboard/rca/rm4100/Config.lb
===================================================================
--- src/mainboard/rca/rm4100/Config.lb (revision 4311)
+++ src/mainboard/rca/rm4100/Config.lb (working copy)
@@ -89,6 +89,9 @@
register "pirqg_routing" = "0x80"
register "pirqh_routing" = "0x0b"
+ register "ide0_enable" = "1"
+ register "ide1_enable" = "1"
+
device pci 1d.0 on end # USB UHCI Controller #1
device pci 1d.1 on end # USB UHCI Controller #2
device pci 1d.2 on end # USB UHCI Controller #3
Index: src/mainboard/nec/powermate2000/Config.lb
===================================================================
--- src/mainboard/nec/powermate2000/Config.lb (revision 4311)
+++ src/mainboard/nec/powermate2000/Config.lb (working copy)
@@ -82,6 +82,9 @@
# end
end
chip southbridge/intel/i82801xx # Southbridge
+ register "ide0_enable" = "1"
+ register "ide1_enable" = "1"
+
device pci 1e.0 on end # PCI bridge
device pci 1f.0 on # ISA/LPC bridge
chip superio/smsc/smscsuperio # Super I/O (SMSC LPC47B27x)
Index: src/mainboard/msi/ms6178/Config.lb
===================================================================
--- src/mainboard/msi/ms6178/Config.lb (revision 4311)
+++ src/mainboard/msi/ms6178/Config.lb (working copy)
@@ -82,6 +82,9 @@
# end
end
chip southbridge/intel/i82801xx # Southbridge
+ register "ide0_enable" = "1"
+ register "ide1_enable" = "1"
+
device pci 1e.0 on end # PCI bridge
device pci 1f.0 on # ISA/LPC bridge
chip superio/winbond/w83627hf # Super I/O
Index: src/mainboard/asus/mew-am/Config.lb
===================================================================
--- src/mainboard/asus/mew-am/Config.lb (revision 4311)
+++ src/mainboard/asus/mew-am/Config.lb (working copy)
@@ -82,6 +82,9 @@
device pci 0.0 on end # Graphics Memory Controller Hub (GMCH)
device pci 1.0 on end # Chipset Graphics Controller (CGC)
chip southbridge/intel/i82801xx # Southbridge
+ register "ide0_enable" = "1"
+ register "ide1_enable" = "1"
+
device pci 1e.0 on end # PCI bridge
device pci 1f.0 on # ISA bridge
chip superio/smsc/smscsuperio # Super I/O
@@ -126,8 +129,6 @@
device pci 1f.3 on end # SMbus
device pci 1f.5 off end # AC'97 audio (N/A, uses CS4280 chip)
device pci 1f.6 off end # AC'97 modem (N/A)
- #register "ide0_enable" = "1"
- #register "ide1_enable" = "1"
end
end
end
Index: src/mainboard/asus/mew-vm/Config.lb
===================================================================
--- src/mainboard/asus/mew-vm/Config.lb (revision 4311)
+++ src/mainboard/asus/mew-vm/Config.lb (working copy)
@@ -103,6 +103,9 @@
#end
end
chip southbridge/intel/i82801xx # Southbridge
+ register "ide0_enable" = "1"
+ register "ide1_enable" = "1"
+
device pci 1e.0 on # PCI Bridge
#chip drivers/pci/onboard
# device pci 1.0 on end
--
coreboot mailing list: [email protected]
http://www.coreboot.org/mailman/listinfo/coreboot
