Author: linux_junkie Date: 2009-05-29 15:45:22 +0200 (Fri, 29 May 2009) New Revision: 4324
Modified: trunk/coreboot-v2/src/mainboard/asus/mew-am/Config.lb trunk/coreboot-v2/src/mainboard/asus/mew-vm/Config.lb trunk/coreboot-v2/src/mainboard/msi/ms6178/Config.lb trunk/coreboot-v2/src/mainboard/nec/powermate2000/Config.lb trunk/coreboot-v2/src/mainboard/rca/rm4100/Config.lb trunk/coreboot-v2/src/mainboard/thomson/ip1000/Config.lb trunk/coreboot-v2/src/southbridge/intel/i82801xx/chip.h trunk/coreboot-v2/src/southbridge/intel/i82801xx/i82801xx_ide.c trunk/coreboot-v2/targets/thomson/ip1000/Config.lb Log: enable/disable IDE 0/1 (Primary/Secondary) interfaces on the i82801xx southbridge. Signed-off-by: Joseph Smith <[email protected]> Acked-by: Ronald G. Minnich <[email protected]> Acked-by: Stefan Reinauer <[email protected]> Modified: trunk/coreboot-v2/src/mainboard/asus/mew-am/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/mew-am/Config.lb 2009-05-29 13:08:27 UTC (rev 4323) +++ trunk/coreboot-v2/src/mainboard/asus/mew-am/Config.lb 2009-05-29 13:45:22 UTC (rev 4324) @@ -82,6 +82,9 @@ device pci 0.0 on end # Graphics Memory Controller Hub (GMCH) device pci 1.0 on end # Chipset Graphics Controller (CGC) chip southbridge/intel/i82801xx # Southbridge + register "ide0_enable" = "1" + register "ide1_enable" = "1" + device pci 1e.0 on end # PCI bridge device pci 1f.0 on # ISA bridge chip superio/smsc/smscsuperio # Super I/O @@ -126,8 +129,6 @@ device pci 1f.3 on end # SMbus device pci 1f.5 off end # AC'97 audio (N/A, uses CS4280 chip) device pci 1f.6 off end # AC'97 modem (N/A) - #register "ide0_enable" = "1" - #register "ide1_enable" = "1" end end end Modified: trunk/coreboot-v2/src/mainboard/asus/mew-vm/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/mew-vm/Config.lb 2009-05-29 13:08:27 UTC (rev 4323) +++ trunk/coreboot-v2/src/mainboard/asus/mew-vm/Config.lb 2009-05-29 13:45:22 UTC (rev 4324) @@ -103,6 +103,9 @@ #end end chip southbridge/intel/i82801xx # Southbridge + register "ide0_enable" = "1" + register "ide1_enable" = "1" + device pci 1e.0 on # PCI Bridge #chip drivers/pci/onboard # device pci 1.0 on end Modified: trunk/coreboot-v2/src/mainboard/msi/ms6178/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms6178/Config.lb 2009-05-29 13:08:27 UTC (rev 4323) +++ trunk/coreboot-v2/src/mainboard/msi/ms6178/Config.lb 2009-05-29 13:45:22 UTC (rev 4324) @@ -82,6 +82,9 @@ # end end chip southbridge/intel/i82801xx # Southbridge + register "ide0_enable" = "1" + register "ide1_enable" = "1" + device pci 1e.0 on end # PCI bridge device pci 1f.0 on # ISA/LPC bridge chip superio/winbond/w83627hf # Super I/O Modified: trunk/coreboot-v2/src/mainboard/nec/powermate2000/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/nec/powermate2000/Config.lb 2009-05-29 13:08:27 UTC (rev 4323) +++ trunk/coreboot-v2/src/mainboard/nec/powermate2000/Config.lb 2009-05-29 13:45:22 UTC (rev 4324) @@ -82,6 +82,9 @@ # end end chip southbridge/intel/i82801xx # Southbridge + register "ide0_enable" = "1" + register "ide1_enable" = "1" + device pci 1e.0 on end # PCI bridge device pci 1f.0 on # ISA/LPC bridge chip superio/smsc/smscsuperio # Super I/O (SMSC LPC47B27x) Modified: trunk/coreboot-v2/src/mainboard/rca/rm4100/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/rca/rm4100/Config.lb 2009-05-29 13:08:27 UTC (rev 4323) +++ trunk/coreboot-v2/src/mainboard/rca/rm4100/Config.lb 2009-05-29 13:45:22 UTC (rev 4324) @@ -89,6 +89,9 @@ register "pirqg_routing" = "0x80" register "pirqh_routing" = "0x0b" + register "ide0_enable" = "1" + register "ide1_enable" = "1" + device pci 1d.0 on end # USB UHCI Controller #1 device pci 1d.1 on end # USB UHCI Controller #2 device pci 1d.2 on end # USB UHCI Controller #3 Modified: trunk/coreboot-v2/src/mainboard/thomson/ip1000/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/thomson/ip1000/Config.lb 2009-05-29 13:08:27 UTC (rev 4323) +++ trunk/coreboot-v2/src/mainboard/thomson/ip1000/Config.lb 2009-05-29 13:45:22 UTC (rev 4324) @@ -89,6 +89,9 @@ register "pirqg_routing" = "0x80" register "pirqh_routing" = "0x0b" + register "ide0_enable" = "1" + register "ide1_enable" = "1" + device pci 1d.0 on end # USB UHCI Controller #1 device pci 1d.1 on end # USB UHCI Controller #2 device pci 1d.2 on end # USB UHCI Controller #3 Modified: trunk/coreboot-v2/src/southbridge/intel/i82801xx/chip.h =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82801xx/chip.h 2009-05-29 13:08:27 UTC (rev 4323) +++ trunk/coreboot-v2/src/southbridge/intel/i82801xx/chip.h 2009-05-29 13:45:22 UTC (rev 4324) @@ -43,6 +43,8 @@ uint8_t pirqf_routing; uint8_t pirqg_routing; uint8_t pirqh_routing; + uint8_t ide0_enable; + uint8_t ide1_enable; }; extern struct chip_operations southbridge_intel_i82801xx_ops; Modified: trunk/coreboot-v2/src/southbridge/intel/i82801xx/i82801xx_ide.c =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82801xx/i82801xx_ide.c 2009-05-29 13:08:27 UTC (rev 4323) +++ trunk/coreboot-v2/src/southbridge/intel/i82801xx/i82801xx_ide.c 2009-05-29 13:45:22 UTC (rev 4324) @@ -27,29 +27,36 @@ #include <device/pci_ids.h> #include "i82801xx.h" +typedef struct southbridge_intel_i82801xx_config config_t; + static void ide_init(struct device *dev) { + /* Get the chip configuration */ + config_t *config = dev->chip_info; + /* TODO: Needs to be tested for compatibility with ICH5(R). */ /* Enable IDE devices so the Linux IDE driver will work. */ uint16_t ideTimingConfig; - int enable_primary = 1; - int enable_secondary = 1; ideTimingConfig = pci_read_config16(dev, IDE_TIM_PRI); ideTimingConfig &= ~IDE_DECODE_ENABLE; - if (enable_primary) { + if (!config || config->ide0_enable) { /* Enable primary IDE interface. */ ideTimingConfig |= IDE_DECODE_ENABLE; - printk_debug("IDE0 "); + printk_debug("IDE0: Primary IDE interface is enabled\n"); + } else { + printk_info("IDE0: Primary IDE interface is disabled\n"); } pci_write_config16(dev, IDE_TIM_PRI, ideTimingConfig); ideTimingConfig = pci_read_config16(dev, IDE_TIM_SEC); ideTimingConfig &= ~IDE_DECODE_ENABLE; - if (enable_secondary) { + if (!config || config->ide1_enable) { /* Enable secondary IDE interface. */ ideTimingConfig |= IDE_DECODE_ENABLE; - printk_debug("IDE1 "); + printk_debug("IDE1: Secondary IDE interface is enabled\n"); + } else { + printk_info("IDE1: Secondary IDE interface is disabled\n"); } pci_write_config16(dev, IDE_TIM_SEC, ideTimingConfig); } Modified: trunk/coreboot-v2/targets/thomson/ip1000/Config.lb =================================================================== --- trunk/coreboot-v2/targets/thomson/ip1000/Config.lb 2009-05-29 13:08:27 UTC (rev 4323) +++ trunk/coreboot-v2/targets/thomson/ip1000/Config.lb 2009-05-29 13:45:22 UTC (rev 4324) @@ -51,7 +51,7 @@ ## ## Request this level of debugging output ## -option DEFAULT_CONSOLE_LOGLEVEL = 9 +option DEFAULT_CONSOLE_LOGLEVEL = 7 romimage "fallback" option USE_FALLBACK_IMAGE = 1 -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
