Author: zbao Date: 2009-06-05 12:00:07 +0200 (Fri, 05 Jun 2009) New Revision: 4339
Modified: trunk/coreboot-v2/src/southbridge/amd/rs690/rs690_pcie.c Log: After I modify the pci_ext_read_config32 and pci_ext_read_config32, the step 6a starts to play its role. Then the system hangs at HDA init. I dont know what the VC1 is. The RPR says "Optional Features (only needed if CMOS option is enabled)" in 5.10.2. Before I know what it is, I think it is better to skip it. Tested on dbm690t. Add comment from Rudolf, " VC is virtual channel. Its used for isochronous transfer of data to sound card. The virtual channel guarantee "on time" delivery. In other words it sets up a channel for data to sound card, which means that that arrivs in time and there will be no interuptions in audio stream. http://www.microsoft.com/whdc/connect/pci/wlp_interrupt.mspx " Signed-off-by: Zheng Bao <[email protected]> Acked-by: Carl-Daniel Hailfinger <[email protected]> Modified: trunk/coreboot-v2/src/southbridge/amd/rs690/rs690_pcie.c =================================================================== --- trunk/coreboot-v2/src/southbridge/amd/rs690/rs690_pcie.c 2009-06-05 00:22:25 UTC (rev 4338) +++ trunk/coreboot-v2/src/southbridge/amd/rs690/rs690_pcie.c 2009-06-05 10:00:07 UTC (rev 4339) @@ -276,6 +276,9 @@ /* step 6a: VCI */ sb_dev = dev_find_slot(0, PCI_DEVFN(8, 0)); if (port == 8) { + /* The code below between #if and #endif causes a hang on HDA init. + * So we skip it. */ +#if 0 /* Clear bits 7:1 */ pci_ext_write_config32(nb_dev, sb_dev, 0x114, 0x3f << 1, 0 << 1); /* Maps Traffic Class 1-7 to VC1 */ @@ -284,7 +287,7 @@ pci_ext_write_config32(nb_dev, sb_dev, 0x120, 7 << 24, 1 << 24); /* Enables VC1 */ pci_ext_write_config32(nb_dev, sb_dev, 0x120, 1 << 31, 1 << 31); -#if 0 + do { reg16 = pci_ext_read_config32(nb_dev, sb_dev, 0x124); reg16 &= 0x2; -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
