On Fri, Jun 5, 2009 at 11:15 AM, ron minnich <[email protected]> wrote: > Ah, well, I want to set up all the RAM for a system to have the kind > of timing that PCM FLASH has. This can't be done with any existing ram > controller, but it could be done with a two-socket opteron system with > an FPGA in one socket . Yes. So you want to just have an artificial delay which varies based on write/read, possibly address if you have some caching, etc.
Very doable, I think. The problem I'm having right now is with unaligned writes. I was hoping that the Opteron would allocate a cache line on a miss to cacheable memory space, and therefore never write partial lines. So far I haven't gotten that to work. Reads are aligned, but partial writes are easy to generate. Am I forgetting something? TLB settings maybe? Opteron settings for allocate on write? Thanks, Myles -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
