Patch AMD Fam10 C2 for errata 327, 344, 346, 354. Removed c2 HT Phy 520a/530a reserved bit. Signed-off-by: Marc Jones Index: coreboot-v2/src/cpu/amd/model_10xxx/defaults.h =================================================================== --- coreboot-v2.orig/src/cpu/amd/model_10xxx/defaults.h 2009-06-05 15:50:02.000000000 -0600 +++ coreboot-v2/src/cpu/amd/model_10xxx/defaults.h 2009-06-05 22:34:13.000000000 -0600 @@ -257,6 +257,11 @@ [5] DisPciCfgCpuMstAbtRsp = 1, [1] SyncFloodOnUsPwDataErr = 1 */ + /* errata 346 - Fam10 C2 + * System software should set F3x188[22] to 1b. */ + { 3, 0x188, AMD_RB_C2, AMD_PTYPE_ALL, + 0x00400000, 0x00400000 }, + /* L3 Control Register */ { 3, 0x1B8, AMD_FAM10_ALL, AMD_PTYPE_ALL, 0x00001000, 0x00001000 }, /* [12] = L3PrivReplEn */ @@ -279,10 +284,106 @@ u32 mask; } fam10_htphy_default[] = { - { 0x520A, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + /* Errata 344 - Fam10 C2 + * System software should set bit 6 of F4x1[9C, 94, 8C, 84]_x[78:70, 68:60]. */ + { 0x60, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + 0x00000040, 0x00000040 }, + { 0x61, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + 0x00000040, 0x00000040 }, + { 0x62, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + 0x00000040, 0x00000040 }, + { 0x63, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + 0x00000040, 0x00000040 }, + { 0x64, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + 0x00000040, 0x00000040 }, + { 0x65, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + 0x00000040, 0x00000040 }, + { 0x66, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + 0x00000040, 0x00000040 }, + { 0x67, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + 0x00000040, 0x00000040 }, + { 0x68, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + 0x00000040, 0x00000040 }, + + { 0x70, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + 0x00000040, 0x00000040 }, + { 0x71, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + 0x00000040, 0x00000040 }, + { 0x72, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + 0x00000040, 0x00000040 }, + { 0x73, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + 0x00000040, 0x00000040 }, + { 0x74, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + 0x00000040, 0x00000040 }, + { 0x75, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + 0x00000040, 0x00000040 }, + { 0x76, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + 0x00000040, 0x00000040 }, + { 0x77, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + 0x00000040, 0x00000040 }, + { 0x78, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + 0x00000040, 0x00000040 }, + + /* Errata 354 - Fam10 C2 + * System software should set bit 6 of F4x1[9C,94,8C,84]_x[58:50, 48:40] for all links. */ + { 0x40, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + 0x00000040, 0x00000040 }, + { 0x41, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + 0x00000040, 0x00000040 }, + { 0x42, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + 0x00000040, 0x00000040 }, + { 0x43, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + 0x00000040, 0x00000040 }, + { 0x44, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + 0x00000040, 0x00000040 }, + { 0x45, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + 0x00000040, 0x00000040 }, + { 0x46, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + 0x00000040, 0x00000040 }, + { 0x47, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + 0x00000040, 0x00000040 }, + { 0x48, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + 0x00000040, 0x00000040 }, + + { 0x50, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + 0x00000040, 0x00000040 }, + { 0x51, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + 0x00000040, 0x00000040 }, + { 0x52, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + 0x00000040, 0x00000040 }, + { 0x53, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + 0x00000040, 0x00000040 }, + { 0x54, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + 0x00000040, 0x00000040 }, + { 0x55, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + 0x00000040, 0x00000040 }, + { 0x56, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + 0x00000040, 0x00000040 }, + { 0x57, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + 0x00000040, 0x00000040 }, + { 0x58, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + 0x00000040, 0x00000040 }, + + /* Errata 327 - Fam10 C2 + * BIOS should set the Link Phy Impedance Register[RttCtl] + * (F4x1[9C, 94, 8C, 84]_x[D0, C0][31:29]) to 010b and + * Link Phy Impedance Register[RttIndex] + * (F4x1[9C, 94, 8C, 84]_x[D0, C0][20:16]) to 00100b */ + { 0xC0, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + 0x40040000, 0xe01F0000 }, + { 0xD0, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + 0x40040000, 0xe01F0000 }, + + { 0x520A, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + 0x00004000, 0x00006000 }, /* HT_PHY_DLL_REG */ + + { 0x530A, AMD_RB_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + 0x00004000, 0x00006000 }, /* HT_PHY_DLL_REG */ + + { 0x520A, AMD_DR_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00004400, 0x00006400 }, /* HT_PHY_DLL_REG */ - { 0x530A, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x530A, AMD_DR_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00004400, 0x00006400 }, /* HT_PHY_DLL_REG */ { 0xCF, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,