Author: oxygene Date: 2009-06-06 13:21:52 +0200 (Sat, 06 Jun 2009) New Revision: 4345
Modified: trunk/coreboot-v2/src/cpu/amd/car/cache_as_ram.inc trunk/coreboot-v2/src/cpu/amd/car/post_cache_as_ram.c trunk/coreboot-v2/src/include/cpu/amd/model_10xxx_msr.h Log: Fix for Erratum 343 for AMD Fam10h CPUs. Signed-off-by: Marco Schmidt <[email protected]> Acked-by: Patrick Georgi <[email protected]> Acked-by: Stefan Reinauer <[email protected]> Modified: trunk/coreboot-v2/src/cpu/amd/car/cache_as_ram.inc =================================================================== --- trunk/coreboot-v2/src/cpu/amd/car/cache_as_ram.inc 2009-06-06 07:19:53 UTC (rev 4344) +++ trunk/coreboot-v2/src/cpu/amd/car/cache_as_ram.inc 2009-06-06 11:21:52 UTC (rev 4345) @@ -27,6 +27,8 @@ /* for CAR_FAM10 */ #define CacheSizeAPStack 0x400 /* 1K */ +#define MSR_FAM10 0xC001102A + #define jmp_if_k8(x) comisd %xmm2, %xmm1; jb x #define CPUID_MASK 0x0ff00f00 @@ -122,6 +124,22 @@ bts $15, %eax wrmsr + /* Erratum 343, RevGuide for Fam10h, Pub#41322 Rev. 3.33 */ + + /* read-address has to be stored in the ecx register */ + movl $MSR_FAM10, %ecx + + /* execute special read command for msr-register. Result is then in the EDX:EAX-registers (MSBs in EDX) */ + rdmsr + + /* Set bit 35 to 1 in EAX */ + bts $35, %eax + + /* write back the modified register EDX:EAX to the MSR specified in ECX */ + wrmsr + + /* Erratum 343 end */ + CAR_FAM10_out_post_errata: /* Set MtrrFixDramModEn for clear fixed mtrr */ Modified: trunk/coreboot-v2/src/cpu/amd/car/post_cache_as_ram.c =================================================================== --- trunk/coreboot-v2/src/cpu/amd/car/post_cache_as_ram.c 2009-06-06 07:19:53 UTC (rev 4344) +++ trunk/coreboot-v2/src/cpu/amd/car/post_cache_as_ram.c 2009-06-06 11:21:52 UTC (rev 4345) @@ -23,8 +23,20 @@ : "S" (src), "D" (dest), "c" ((bytes)>>2) ); } +/* Disable Erratum 343 Workaround, see RevGuide for Fam10h, Pub#41322 Rev 3.33 */ +static void vErrata343(void) +{ + msr_t msr; + unsigned int uiMask = 0xFFFFFFF7; +#ifdef BU_CFG2_MSR + msr = rdmsr(BU_CFG2_MSR); + msr.hi &= uiMask; // set bit 35 to 0 + wrmsr(BU_CFG2_MSR, msr); +#endif +} + static void post_cache_as_ram(void) { @@ -56,6 +68,8 @@ print_debug("Copying data from cache to RAM -- switching to use RAM as stack... "); /* from here don't store more data in CAR */ + vErrata343(); + #if 0 __asm__ volatile ( "pushl %eax\n\t" Modified: trunk/coreboot-v2/src/include/cpu/amd/model_10xxx_msr.h =================================================================== --- trunk/coreboot-v2/src/include/cpu/amd/model_10xxx_msr.h 2009-06-06 07:19:53 UTC (rev 4344) +++ trunk/coreboot-v2/src/include/cpu/amd/model_10xxx_msr.h 2009-06-06 11:21:52 UTC (rev 4345) @@ -26,6 +26,7 @@ #define IC_CFG_MSR 0xC0011021 #define DC_CFG_MSR 0xC0011022 #define BU_CFG_MSR 0xC0011023 +#define BU_CFG2_MSR 0xC001102A #define CPU_ID_FEATURES_MSR 0xC0011004 #define CPU_ID_HYPER_EXT_FEATURES 0xC001100d -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
