> Myles, > > Maybe leave the MTRR off until you get it working. I think that you > can leave it in CAR mode until you have tested that the memory is > working.
I'm trying that now. > I assume you are very failiar with the FAM10 BKDG 2.6.4.1.1 DRAM and > MMIO Memory Space. I've been reading it, but it seems like you can never be familiar enough with data sheets and other docs :) > Can you successfully access the memory as MMIO, F1x[BC:80] before > trying F1x[1, 0][7C:40] DRAM address setup? I am not sure what will > happen with a DRAM access that tries to go out a non-coherent link. I was hoping that the DRAM address registers are all disabled before RAM init. I'll look again to make sure. Thanks, Myles -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
