> > the way SMP works, the BSP sets up its ram. At that point, the APs can > > use the BSP ram. That's why APs have a stack in the first place. > > > > APs have a working stack when they are setting up their own RAM. > > > The way this works on amd64 is that the AP comes up, goes to cache as > ram, finds it is an AP and goes to sleep again. > Then it wakes up again in stage2 when the BSP sends an IPI. At this > point (at least remote) RAM is available. They never set up their own > ram (in terms of Jedec init, or setting up a ram controller), but only > have to clear it, in case of ECC memory.
OK. I'd thought that they each initialized their own RAM, then went to sleep. Thanks. Myles -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
