-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Hello,
I think for SB600 only very little is needed to get a chance that S3 will work. Please check the patch for AMD board dbm690t The patch is just an example and compile tested! Some (expected) problems: 1) the code which save/restore might not work - please check it! 2) the SuperIO chip might cut of the power to ram (for IT8712 check the 3vsb routine) 3) it will work on singlecore, dualcore maybe 4) it may corrupt CAR address area (it does not matter because not even ROM is there) Just a cert of origin: (not think this will go for SVN right now) Signed-off-by: Rudolf Marek <[email protected]> Rudolf -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.9 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org iEYEARECAAYFAko/6v8ACgkQ3J9wPJqZRNWBRgCfRqkrHxvTRz89n+1ya/YacPio SkQAoJGgFwguIi59ma0ro3BcaFJt0E+5 =UphE -----END PGP SIGNATURE-----
Index: src/southbridge/amd/sb600/sb600.h
===================================================================
--- src/southbridge/amd/sb600/sb600.h (revision 4367)
+++ src/southbridge/amd/sb600/sb600.h (working copy)
@@ -24,6 +24,8 @@
#include "chip.h"
/* Power management index/data registers */
+#define BIOSRAM_INDEX 0xcd4
+#define BIOSRAM_DATA 0xcd5
#define PM_INDEX 0xcd6
#define PM_DATA 0xcd7
#define PM2_INDEX 0xcd0
Index: src/southbridge/amd/sb600/sb600_early_setup.c
===================================================================
--- src/southbridge/amd/sb600/sb600_early_setup.c (revision 4367)
+++ src/southbridge/amd/sb600/sb600_early_setup.c (working copy)
@@ -23,8 +23,8 @@
#define SMBUS_IO_BASE 0x1000 /* Is it a temporary SMBus I/O base address? */
/*SIZE 0x40 */
+#define S3_NVRAM_EARLY 1
-
static void pmio_write(u8 reg, u8 value)
{
outb(reg, PM_INDEX);
@@ -681,3 +681,29 @@
return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
}
+int s3_save_nvram_early(u32 dword, int size, int nvram_pos) {
+ int i;
+ printk_debug("Writing %x of size %d to nvram pos: %d\n", dword, size, nvram_pos);
+
+ for (i = 0; i<size; i++) {
+ outb(nvram_pos, BIOSRAM_INDEX);
+ outb((dword >>(8 * i)) & 0xff , BIOSRAM_DATA);
+ nvram_pos++;
+ }
+
+ return nvram_pos;
+}
+
+int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos) {
+ u32 data = *old_dword;
+ int i;
+ for (i = 0; i<size; i++) {
+ outb(nvram_pos, BIOSRAM_INDEX);
+ data &= ~(0xff << (i * 8));
+ data |= inb(BIOSRAM_DATA) << (i *8);
+ nvram_pos++;
+ }
+ *old_dword = data;
+ printk_debug("Loading %x of size %d to nvram pos:%d\n", * old_dword, size, nvram_pos-size);
+ return nvram_pos;
+}
Index: src/mainboard/amd/dbm690t/Options.lb
===================================================================
--- src/mainboard/amd/dbm690t/Options.lb (revision 4367)
+++ src/mainboard/amd/dbm690t/Options.lb (working copy)
@@ -24,6 +24,7 @@
uses HAVE_PIRQ_TABLE
uses HAVE_ACPI_TABLES
uses HAVE_ACPI_RESUME
+uses CONFIG_LB_MEM_TOPK
uses USE_FALLBACK_IMAGE
uses HAVE_FALLBACK_BOOT
uses HAVE_HARD_RESET
@@ -225,7 +226,7 @@
##
## coreboot C code runs at this location in RAM
##
-default _RAMBASE=0x00004000
+default _RAMBASE=0x1F00000
##
## Load the payload from the ROM
@@ -300,6 +301,9 @@
default CONFIG_GFXUMA=1
default HAVE_MAINBOARD_RESOURCES=1
+default HAVE_ACPI_RESUME=1
+default CONFIG_LB_MEM_TOPK = 32768
+
### End Options.lb
#
# CBFS
Index: src/mainboard/amd/dbm690t/mainboard.c
===================================================================
--- src/mainboard/amd/dbm690t/mainboard.c (revision 4367)
+++ src/mainboard/amd/dbm690t/mainboard.c (working copy)
@@ -261,6 +261,14 @@
lb_add_memory_range(mem, LB_MEM_RESERVED,
uma_memory_base, uma_memory_size);
#endif
+
+#if HAVE_ACPI_RESUME == 1
+ lb_add_memory_range(mem, LB_MEM_RESERVED,
+ _RAMBASE, ((CONFIG_LB_MEM_TOPK<<10) - _RAMBASE));
+ lb_add_memory_range(mem, LB_MEM_RESERVED,
+ DCACHE_RAM_BASE, DCACHE_RAM_SIZE);
+#endif
+
}
struct chip_operations mainboard_ops = {
Index: src/arch/i386/boot/acpi.c
===================================================================
--- src/arch/i386/boot/acpi.c (revision 4367)
+++ src/arch/i386/boot/acpi.c (working copy)
@@ -395,7 +395,7 @@
{
void *wake_vec;
-#if 0
+#if 1
#if MEM_TRAIN_SEQ != 0
#error "So far it works on AMD and MEM_TRAIN_SEQ == 0"
#endif
s3_sb600.patch.sig
Description: Binary data
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