On Tue, Jun 23, 2009 at 12:42 PM, Thomas JOURDAN <[email protected]>wrote:
> Hi > > This series of patches add support in coreboot-v2 for the Intel Eagle > Heights evaluation board Welcome to the project! http://www.coreboot.org/Development_Guidelines#Sign-off_Procedure If you sign off your patches they can be reviewed, acked, and committed. > > Things broken : > * reset (the config file only has a fallback image and don't really > understand the concept of failover / fallback / normal image) > * vga rom -> The evaluation board comes with a PCIe 1x Matrox G550 > graphics card. Coreboot fails to execute the vga rom (either x86emu, > yabel or real mode). There is an exception 0x06 and everything will > freeze. It could be the loadall instruction > (http://en.wikipedia.org/wiki/LOADALL). I'll investigate tomorrow with > a probe to understand what happens. > You could try having SeaBIOS enable your ROM. There have been several cases where SeaBIOS was less picky than the others. http://www.coreboot.org/SeaBIOS > - the mmconf is hardcoded to 0xE0000000 but I don't understand how the > resource allocate can properly handle it. If you change the mmconf > address in the northbridge code, don't forget to adjust the associated > motherboard resource in the DSDT. The current resource allocator can't handle it. If you want to test the new one, you can apply the patches from this mail: http://www.coreboot.org/pipermail/coreboot/2009-May/048928.html Just make sure that your mmconf register gets hardcoded and set in the read_resources function with the flags IORESOURCE_FIXED | IORESOURCE_ASSIGNED The new allocator avoids fixed resources, but can only allocate to one side of them. I recommend putting your resource as high as you can. Make sure limit > base. If you send me a log from before and after the patch it'll help both of us :) For lucky people (like me) who owns the board and wants to give it a > try, flashrom won't work with the original bios. The board has a > SST49LF008A (FWH 1MB) on a PLCC32 socket, which is cool. But the > default bios will lock down half of the chip. Flashrom will fail to > properly detect it. To bypass this, I forced flashrom to detect the > chip as a 49LF004A (512KB). This way, I can write a first 512KB > coreboot file. After, no more problems, the full 1MB are available in > flashrom. Of course, no problem if you use an external flasher. > Very nice. Thanks, Myles
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