I am not sure about this patch. Not sure to add signed-off-by line.
Don't ack it before review and say something.

My board is Fam10 + 1 HT SouthBridge. It is close to dbm690t. So I
set HT_CHAIN_UNITID_BASE as 0 and HT_CHAIN_END_UNITID_BASE as 1, even
though I dont know well what they actually are. Base on currently fam10
code, I have skip some code, otherwise the HT link can not be set up
correctly. It is pretty like a workaround and my board can work in
1.8GHz (HT3). Doesn't the code in repository cover the mode of
one HT processor + 1 HT SB device?

Index: src/northbridge/amd/amdht/h3finit.c
===================================================================
--- src/northbridge/amd/amdht/h3finit.c	(revision 503)
+++ src/northbridge/amd/amdht/h3finit.c	(working copy)
@@ -1104,6 +1104,7 @@
 				AmdPCIRead(currentPtr, &temp);
 			} while (!IS_HT_SLAVE_CAPABILITY(temp));
 
+#if (HT_CHAIN_UNITID_BASE != 0)
 			AmdPCIReadBits(currentPtr, 25, 21, &unitIDcnt);
 			if ((unitIDcnt + currentBUID > 31) || ((secBus == 0) && (unitIDcnt + currentBUID > 24)))
 			{
@@ -1145,7 +1146,7 @@
 				STOP_HERE;
 				break;
 			}
-
+#endif
 			AmdPCIReadBits(currentPtr, 26, 26, &temp);
 			pDat->PortList[pDat->TotalLinks*2+1].Link = (u8)temp;
 			pDat->PortList[pDat->TotalLinks*2+1].Pointer = currentPtr;
@@ -1156,6 +1157,11 @@
 			depth++;
 			pDat->TotalLinks++;
 			currentBUID += unitIDcnt;
+#if HT_CHAIN_UNITID_BASE == 0
+			STOP_HERE;
+			break;
+#endif
+
 		}
 		if (pDat->HtBlock->AMD_CB_EventNotify)
 		{