Index: src/mainboard/via/epia-n/Config.lb
===================================================================
--- src/mainboard/via/epia-n/Config.lb	(revision 1)
+++ src/mainboard/via/epia-n/Config.lb	(working copy)
@@ -116,22 +116,15 @@
 dir /pc80
 config chip.h
 
-chip northbridge/via/cn400			# Northbridge
-
-  device apic_cluster 0 on			# APIC cluster
-    chip cpu/via/model_c3			# VIA C3
-      device apic 0 on end			# APIC
-    end
-  end
-
-  device pci_domain 0 on			# PCI domain
-    device pci 0.0 on end			# AGP Bridge
-    device pci 0.1 on end			# Error Reporting
-    device pci 0.2 on end			# Host Bus Control
-    device pci 0.3 on end			# Memory Controller
-    device pci 0.4 on end			# Power Management
-    device pci 0.7 on end			# V-Link Controller
-    device pci 1.0 on end			# PCI Bridge
+chip northbridge/via/cn400				# Northbridge
+  device pci_domain 0 on				# PCI domain
+    device pci 0.0 on end				# AGP Bridge
+    device pci 0.1 on end				# Error Reporting
+    device pci 0.2 on end				# Host Bus Control
+    device pci 0.3 on end				# Memory Controller
+    device pci 0.4 on end				# Power Management
+    device pci 0.7 on end				# V-Link Controller
+    device pci 1.0 on end				# PCI Bridge
     chip southbridge/via/vt8237r		# Southbridge
       # Enable both IDE channels.
       register "ide0_enable" = "1"
@@ -190,8 +183,13 @@
         end
       end
       device pci 11.5 off end			# AC'97 audio
-      # device pci 11.6 off end			# AC'97 Modem
+      device pci 11.6 off end			# AC'97 Modem
       device pci 12.0 on end			# Ethernet
     end
   end
+  device apic_cluster 0 on				# APIC cluster
+    chip cpu/via/model_c3				# VIA C3
+      device apic 0 on end				# APIC
+    end
+  end
 end
Index: src/northbridge/via/cn400/raminit.c
===================================================================
--- src/northbridge/via/cn400/raminit.c	(revision 1)
+++ src/northbridge/via/cn400/raminit.c	(working copy)
@@ -265,8 +265,6 @@
 	else if( b & 0x08) c = 0x01;    	// 32MB
 	else c = 0x01;                  	// Error, use default
 
-	//print_val("\r\nBank 0 (*32 Mb) ",c);
-
 	// set bank zero size
 	pci_write_config8(ctrl.d0f3, 0x40, c);
 	
@@ -278,7 +276,6 @@
 	{
 		c <<=1;
 		bank |= 0x80;
-		//print_val("\r\nTotal Memory (*32 Mb) ",c);
 	}
 /*	else
 	{
@@ -790,20 +787,4 @@
 	pci_write_config16(ctrl.d0f3, 0xa0, (1 << 15));
 	pci_write_config16(ctrl.d0f3, 0xa4, 0x0010);
 	
-	/* Graphics Control Basic Init. */
-	//pci_write_config8(ctrl.d0f3, 0xb0, 0xFf);
-	//pci_write_config8(ctrl.d0f3, 0xb1, 0xAA);
-	//pci_write_config8(ctrl.d0f3, 0xb2, 0xAA);
-	//pci_write_config8(ctrl.d0f3, 0xb3, 0x5A);
-	//pci_write_config8(ctrl.d0f3, 0xb4, 0x0f);
-	
-	/* AGP Controller Interface Basic Init */
-	//pci_write_config8(ctrl.d0f3, 0xc0, 0x3b);
-	
-	/* VGA device, Basic frame Buffer Init. */
-	//pci_write_config8(ctrl.d0f3, 0xa0, 0x01);
-	/* Bit 7 = Enable VGA When Set to 1 */
-	//pci_write_config8(ctrl.d0f3, 0xa1, 0xef);
-	//pci_write_config8(ctrl.d0f3, 0xa4, 0x00);
-
 }	
Index: src/northbridge/via/cn400/northbridge.c
===================================================================
--- src/northbridge/via/cn400/northbridge.c	(revision 1)
+++ src/northbridge/via/cn400/northbridge.c	(working copy)
@@ -42,6 +42,13 @@
 
 	printk_spew("Entering cn400 memctrl_init.\n");
 	
+	/* Setup Low Memory Top */
+	ranks = pci_read_config8(dev, 0x47);
+	reg16 = (((u16)(ranks - 1) << 5) & 0xFFF0) | 0x0010;
+	
+	pci_write_config16(dev, 0x84, reg16);
+	printk_spew("Low Top Address = 0x%04X\n", reg16);
+
 	/* Set up the VGA framebuffer size. */
 	reg16 = (log2(CONFIG_VIDEO_MB) << 12) | (1 << 15);
 	pci_write_config16(dev, 0xa0, reg16);
@@ -50,11 +57,12 @@
 	pci_write_config8(dev, 0xa2, 0x44);
 
 	for (ranks = 0x4b; ranks >= 0x48; ranks--) {
-		if (pci_read_config8(dev, ranks)) {
+		if ((pci_read_config8(dev, ranks))) {
 			ranks -= 0x48;
 			break;
 		}
 	}
+	
 	if (ranks == 0x47)
 		ranks = 0x00;
 	reg16 = 0xaaf0;
@@ -91,8 +99,11 @@
 }
 
 static const struct device_operations memctrl_operations = {
-	.read_resources = cn400_noop,
-	.init           = memctrl_init,
+	.read_resources   = cn400_noop,
+	.set_resources    = cn400_noop,
+	.enable_resources = cn400_noop,
+	.init             = memctrl_init,
+	.ops_pci          = 0,
 };
 
 static const struct pci_driver memctrl_driver __pci_driver = {
@@ -129,10 +140,9 @@
 
 	if (!sizek)
 		return;
-
 	resource = new_resource(dev, index);
-	resource->base = ((resource_t) basek) << 10;
-	resource->size = ((resource_t) sizek) << 10;
+	resource->base = (resource_t) (basek << 10);
+	resource->size = (resource_t) (sizek << 10);
 	resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE |
 	    IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
 }
@@ -150,24 +160,23 @@
 
 static u32 find_pci_tolm(struct bus *bus)
 {
-	struct resource *min;
+	struct resource *min = NULL;
 	u32 tolm;
 
-	print_debug("Entering CN400 find_pci_tolm\n");
+	printk_spew("Entering CN400 find_pci_tolm\n");
 
-	min = 0;
 	search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM,
 			     tolm_test, &min);
 	tolm = 0xffffffffUL;
 	if (min && tolm > min->base)
 		tolm = min->base;
 
-	print_debug("Leaving find_pci_tolm\n");
+	printk_spew("Leaving CN400 find_pci_tolm\n");
 
 	return tolm;
 }
 
-#if HAVE_HIGH_TABLES==1
+#if CONFIG_HAVE_HIGH_TABLES==1
 /* maximum size of high tables in KB */
 #define HIGH_TABLES_SIZE 64
 extern uint64_t high_tables_base, high_tables_size;
@@ -176,7 +185,7 @@
 static void cn400_domain_set_resources(device_t dev)
 {
 	/* The order is important to find the correct RAM size. */
-	static const u8 ramregs[] = { 0x43, 0x42, 0x41, 0x40 };
+	//static const u8 ramregs[] = { 0x43, 0x42, 0x41, 0x40 };
 	device_t mc_dev;
 	u32 pci_tolm;
 
@@ -191,29 +200,21 @@
 		unsigned char rambits;
 		int i, idx;
 
-		/*
-		 * Once the register value is not zero, the RAM size is
-		 * this register's value multiply 64 * 1024 * 1024.
-		 */
-		for (rambits = 0, i = 0; i < ARRAY_SIZE(ramregs); i++) {
-			rambits = pci_read_config8(mc_dev, ramregs[i]);
-			if (rambits != 0)
-				break;
-		}
-
-		tomk = rambits * 64 * 1024;
-		printk_spew("tomk is 0x%x\n", tomk);
+		rambits = pci_read_config8(mc_dev, 0x47);
+		tomk = rambits * 32 * 1024;
 		/* Compute the Top Of Low Memory (TOLM), in Kb. */
 		tolmk = pci_tolm >> 10;
+		printk_spew("tomk is 0x%x, tolmk is 0x%08X\n", tomk, tolmk);
 		if (tolmk >= tomk) {
 			/* The PCI hole does does not overlap the memory. */
 			tolmk = tomk;
 		}
 
-#if HAVE_HIGH_TABLES == 1
-		high_tables_base = (tolmk - HIGH_TABLES_SIZE) * 1024;
-		high_tables_size = HIGH_TABLES_SIZE* 1024;
-		printk_debug("tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n", tomk*1024, high_tables_base, high_tables_size);
+#if CONFIG_HAVE_HIGH_TABLES == 1
+		/* Locate the High Tables at the Top of Low Memory below the Video RAM */
+		high_tables_base = (uint64_t) (tolmk - (CONFIG_VIDEO_MB *1024) - HIGH_TABLES_SIZE) * 1024;
+		high_tables_size = (uint64_t) HIGH_TABLES_SIZE* 1024;
+		printk_spew("tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n", tomk*1024, high_tables_base, high_tables_size);
 #endif
 
 		/* Report the memory regions. */