On Monday 13 July 2009 20:32:46 Harald Gutmann wrote: > 4. assume you did everything right and claim that it is value 0x72 > (hopefully you got it right with the pci-register-endianness and the > address number). ;) Okay, this was for sure wrong, as I read the line number instead the pci- register number. It has to be 0x52 instead 0x72.
Attached is a little patch, which is not working on different hardware than mine, as some values are hard-coded. Also the place I patched that stuff is totally "wrong". This patch works for me on my hardware: [ 2.256143] hda: UDMA/133 mode selected [ 2.256333] hdb: UDMA/66 mode selected There are a few things which I need to figure out to get this stuff working like it should: [*] Where shall I add the patch? src/southbridge/nvidia/mcp55/mcp55.c in mcp55_enable case device = IDE? some better/different suggestions? [*] How to figure out the UDMA modes supported by the attached devices in coreboot? As this is according to IDE devices which can be changed at any time, it would be necessary to check for supported UDMA modes on run-time. Any suggestions/ideas/further reading documents/... is welcome. Kind regards, Harald Gutmann
Index: mptable.c
===================================================================
--- mptable.c (revision 4397)
+++ mptable.c (working copy)
@@ -93,6 +93,19 @@
pci_write_config32(dev, 0x84, 0x200018d2);
}
}
+ //TODO: Wrong place!
+ {
+ device_t dev;
+ dev = dev_find_slot(bus_mcp55[0], PCI_DEVFN(sbdn+ 0x4,0));
+ if (dev) {
+ if(pci_read_config8(dev, 0x52) == 0x00){
+ pci_write_config8(dev, 0x5e, 0x99);
+ //TODO: check for UDMA modes and set bits * this is hardcoded
+ pci_write_config8(dev, 0x62, 0xc5);
+ pci_write_config8(dev, 0x63, 0xc7);
+ }
+ }
+ }
/*I/O Ints: Type Trigger Polarity Bus ID IRQ APIC ID PIN# */
smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_mcp55, 0x0);
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