Author: stepan Date: 2009-07-21 23:58:20 +0200 (Tue, 21 Jul 2009) New Revision: 4458
Added: trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/acpi/i945_pci_irqs.asl trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/acpi/ich7_pci_irqs.asl Removed: trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/acpi/cpu.asl trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/acpi/globalnvs.asl trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/acpi/sleepstates.asl Modified: trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/Config.lb trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/Options.lb trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/acpi_tables.c trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/auto.c trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/cmos.layout trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/dsdt.asl trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/fadt.c trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/mainboard.c trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/mainboard_smi.c Log: Kontron updates, get board up to date with i945 and ich7 updates. Move interrupt routing to mainboard specific code. Signed-off-by: Stefan Reinauer <[email protected]> Acked-by: Peter Stuge <[email protected]> Modified: trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/Config.lb 2009-07-21 21:57:11 UTC (rev 4457) +++ trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/Config.lb 2009-07-21 21:58:20 UTC (rev 4458) @@ -28,8 +28,10 @@ ## default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 64 * 1024 +## +## Image size calculation +## + include /config/nofailovercalculation.lb ## @@ -175,7 +177,7 @@ register "ide_legacy_combined" = "0x1" register "ide_enable_primary" = "0x1" - register "ide_enable_secondary" = "0x0" + register "ide_enable_secondary" = "0x1" register "sata_ahci" = "0x0" device pci 1b.0 on end # High Definition Audio Modified: trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/Options.lb 2009-07-21 21:57:11 UTC (rev 4457) +++ trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/Options.lb 2009-07-21 21:58:20 UTC (rev 4458) @@ -80,8 +80,7 @@ uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID # Timers -uses CONFIG_UDELAY_TSC -uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 +uses CONFIG_UDELAY_LAPIC # Console uses CONFIG_CONSOLE_SERIAL8250 uses CONFIG_TTYS0_BAUD @@ -131,10 +130,8 @@ ## ## Delay timer options -## Use timer2 ## -default CONFIG_UDELAY_TSC=1 -default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 +default CONFIG_UDELAY_LAPIC=1 ## ## Build code to reset the motherboard from coreboot @@ -176,6 +173,7 @@ ## default CONFIG_HAVE_ACPI_TABLES=1 default CONFIG_HAVE_MAINBOARD_RESOURCES=1 +default CONFIG_HAVE_ACPI_RESUME=1 ## ## Build code to export a CMOS option table @@ -217,6 +215,13 @@ default CONFIG_USE_PRINTK_IN_CAR=1 ## +## Execute In Place settings +## + +default CONFIG_XIP_ROM_SIZE = 128 * 1024 +default CONFIG_XIP_ROM_BASE = ( CONFIG_ROMBASE - CONFIG_XIP_ROM_SIZE + CONFIG_ROM_IMAGE_SIZE ) + +## ## Build code to setup a generic IOAPIC ## default CONFIG_IOAPIC=1 @@ -232,12 +237,12 @@ ### ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default CONFIG_ROM_IMAGE_SIZE = 65536 +default CONFIG_ROM_IMAGE_SIZE = 0x10000 ## -## Use a small 8K stack +## Use a small 32K stack ## -default CONFIG_STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x8000 ## ## Use a small 32K heap Deleted: trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/acpi/cpu.asl =================================================================== --- trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/acpi/cpu.asl 2009-07-21 21:57:11 UTC (rev 4457) +++ trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/acpi/cpu.asl 2009-07-21 21:58:20 UTC (rev 4458) @@ -1,51 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -/* Intel Core (2) Duo CPU node support - * - * Note: The ACPI P_BLK on the ICH7 (and probably others) lives at - * PMBASE + 0x10, and it's 0x06 bytes long. On ICH8 it's 8 bytes. - * - * The second CPU core does not need its own P_BLK. - */ - -Scope(\_PR) -{ - Processor( - CPU1, // name of cpu/core 0 - 1, // numeric id of cpu/core - 0x510, // ACPI P_BLK base address - 6 // ACPI P_BLK size - ) - { - // TODO: _PDT - } - - Processor( - CPU2, // name of cpu/core 1 - 2, // numeric id of cpu/core 1 - 0, // ACPI P_BLK base address - 0) // ACPI P_BLK size - { - // TODO: _PDT - } -} // End _PR - Deleted: trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/acpi/globalnvs.asl =================================================================== --- trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/acpi/globalnvs.asl 2009-07-21 21:57:11 UTC (rev 4457) +++ trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/acpi/globalnvs.asl 2009-07-21 21:58:20 UTC (rev 4458) @@ -1,42 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -/* Global Variables */ - -Name(\PICM,0) // IOAPIC/8259 - -/* Global ACPI memory region. This region is used for passing information - * between coreboot (aka "the system bios"), ACPI, and the SMI handler. - * Since we don't know where this will end up in memory at ACPI compile time, - * we have to fix it up in coreboot's ACPI creation phase. - */ - - -OperationRegion (GNVS, SystemMemory, 0xC0DEBABE, 0xFF) -Field (GNVS, ByteAcc, NoLock, Preserve) -{ - Offset (0x00), - OSYS, 16, // 0x00 Operating System - SMIF, 8, // 0x02 SMI function - Offset (0x10), - MPEN, 8, // 0x10 Multi Processor Enable - -} Added: trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/acpi/i945_pci_irqs.asl =================================================================== --- trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/acpi/i945_pci_irqs.asl (rev 0) +++ trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/acpi/i945_pci_irqs.asl 2009-07-21 21:58:20 UTC (rev 4458) @@ -0,0 +1,88 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +/* This is board specific information: IRQ routing for the + * i945 + */ + + +// PCI Interrupt Routing +Method(_PRT) +{ + If (PICM) { + Return (Package() { + // PCIe Graphics 0:1.0 + Package() { 0x0001ffff, 0, 0, 16 }, + Package() { 0x0001ffff, 1, 0, 17 }, + Package() { 0x0001ffff, 2, 0, 18 }, + Package() { 0x0001ffff, 3, 0, 19 }, + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, 0, 16 }, + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, 0, 16 }, + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, 0, 16 }, + Package() { 0x001cffff, 1, 0, 17 }, + Package() { 0x001cffff, 2, 0, 18 }, + Package() { 0x001cffff, 3, 0, 19 }, + // USB and EHCI 0:1d.x + Package() { 0x001dffff, 0, 0, 23 }, + Package() { 0x001dffff, 1, 0, 19 }, + Package() { 0x001dffff, 2, 0, 18 }, + Package() { 0x001dffff, 3, 0, 16 }, + // AC97/IDE 0:1e.2, 0:1e.3 + Package() { 0x001effff, 0, 0, 17 }, + Package() { 0x001effff, 1, 0, 20 }, + // LPC device 0:1f.0 + Package() { 0x001fffff, 0, 0, 18 }, + Package() { 0x001fffff, 1, 0, 19}, + }) + } Else { + Return (Package() { + // PCIe Graphics 0:1.0 + Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, + // USB and EHCI 0:1d.x + Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, + Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, + Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKA, 0 }, + // AC97/IDE 0:1e.2, 0:1e.3 + Package() { 0x001effff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001effff, 1, \_SB.PCI0.LPCB.LNKE, 0 }, + // LPC device 0:1f.0 + Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, + }) + } +} + Added: trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/acpi/ich7_pci_irqs.asl =================================================================== --- trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/acpi/ich7_pci_irqs.asl (rev 0) +++ trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/acpi/ich7_pci_irqs.asl 2009-07-21 21:58:20 UTC (rev 4458) @@ -0,0 +1,105 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +/* This is board specific information: IRQ routing for the + * 0:1e.0 PCI bridge of the ICH7 + */ + +If (PICM) { + Return (Package() { + Package() { 0x0000ffff, 0, 0, 16}, + + Package() { 0x0001ffff, 0, 0, 20}, + Package() { 0x0001ffff, 1, 0, 21}, + Package() { 0x0001ffff, 2, 0, 22}, + Package() { 0x0001ffff, 3, 0, 23}, + + Package() { 0x0002ffff, 0, 0, 21}, + Package() { 0x0002ffff, 1, 0, 22}, + Package() { 0x0002ffff, 2, 0, 23}, + Package() { 0x0002ffff, 3, 0, 20}, + + Package() { 0x0003ffff, 0, 0, 22}, + Package() { 0x0003ffff, 1, 0, 23}, + Package() { 0x0003ffff, 2, 0, 20}, + Package() { 0x0003ffff, 3, 0, 21}, + + Package() { 0x0004ffff, 0, 0, 23}, + Package() { 0x0004ffff, 1, 0, 20}, + Package() { 0x0004ffff, 2, 0, 21}, + Package() { 0x0004ffff, 3, 0, 22}, + + Package() { 0x0005ffff, 0, 0, 19}, + Package() { 0x0005ffff, 1, 0, 18}, + Package() { 0x0005ffff, 2, 0, 17}, + Package() { 0x0005ffff, 3, 0, 16}, + + Package() { 0x0006ffff, 0, 0, 18}, + Package() { 0x0006ffff, 1, 0, 17}, + Package() { 0x0006ffff, 2, 0, 16}, + Package() { 0x0006ffff, 3, 0, 19}, + + Package() { 0x0009ffff, 0, 0, 21}, + Package() { 0x0009ffff, 1, 0, 22}, + Package() { 0x0009ffff, 2, 0, 23}, + Package() { 0x0009ffff, 3, 0, 20}, + }) +} Else { + Return (Package() { + Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKA, 0}, + + Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKE, 0}, + Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKF, 0}, + Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKG, 0}, + Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKH, 0}, + + Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKF, 0}, + Package() { 0x0002ffff, 1, \_SB.PCI0.LPCB.LNKG, 0}, + Package() { 0x0002ffff, 2, \_SB.PCI0.LPCB.LNKH, 0}, + Package() { 0x0002ffff, 3, \_SB.PCI0.LPCB.LNKE, 0}, + + Package() { 0x0003ffff, 0, \_SB.PCI0.LPCB.LNKG, 0}, + Package() { 0x0003ffff, 1, \_SB.PCI0.LPCB.LNKH, 0}, + Package() { 0x0003ffff, 2, \_SB.PCI0.LPCB.LNKE, 0}, + Package() { 0x0003ffff, 3, \_SB.PCI0.LPCB.LNKF, 0}, + + Package() { 0x0004ffff, 0, \_SB.PCI0.LPCB.LNKH, 0}, + Package() { 0x0004ffff, 1, \_SB.PCI0.LPCB.LNKE, 0}, + Package() { 0x0004ffff, 2, \_SB.PCI0.LPCB.LNKF, 0}, + Package() { 0x0004ffff, 3, \_SB.PCI0.LPCB.LNKG, 0}, + + Package() { 0x0005ffff, 0, \_SB.PCI0.LPCB.LNKD, 0}, + Package() { 0x0005ffff, 1, \_SB.PCI0.LPCB.LNKC, 0}, + Package() { 0x0005ffff, 2, \_SB.PCI0.LPCB.LNKB, 0}, + Package() { 0x0005ffff, 3, \_SB.PCI0.LPCB.LNKA, 0}, + + Package() { 0x0006ffff, 0, \_SB.PCI0.LPCB.LNKC, 0}, + Package() { 0x0006ffff, 1, \_SB.PCI0.LPCB.LNKB, 0}, + Package() { 0x0006ffff, 2, \_SB.PCI0.LPCB.LNKA, 0}, + Package() { 0x0006ffff, 3, \_SB.PCI0.LPCB.LNKD, 0}, + + Package() { 0x0009ffff, 0, \_SB.PCI0.LPCB.LNKF, 0}, + Package() { 0x0009ffff, 1, \_SB.PCI0.LPCB.LNKG, 0}, + Package() { 0x0009ffff, 2, \_SB.PCI0.LPCB.LNKH, 0}, + Package() { 0x0009ffff, 3, \_SB.PCI0.LPCB.LNKE, 0}, + }) +} + Deleted: trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/acpi/sleepstates.asl =================================================================== --- trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/acpi/sleepstates.asl 2009-07-21 21:57:11 UTC (rev 4457) +++ trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/acpi/sleepstates.asl 2009-07-21 21:58:20 UTC (rev 4458) @@ -1,27 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -Name(\_S0, Package(4){0x0,0x0,0,0}) -Name(\_S1, Package(4){0x1,0x0,0,0}) -Name(\_S3, Package(4){0x5,0x0,0,0}) -Name(\_S4, Package(4){0x6,0x0,0,0}) -Name(\_S5, Package(4){0x7,0x0,0,0}) - Modified: trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/acpi_tables.c =================================================================== --- trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/acpi_tables.c 2009-07-21 21:57:11 UTC (rev 4457) +++ trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/acpi_tables.c 2009-07-21 21:58:20 UTC (rev 4458) @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2008 coresystems GmbH + * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -19,16 +19,28 @@ * MA 02110-1301 USA */ +#include <types.h> #include <string.h> #include <console/console.h> #include <arch/acpi.h> +#include <arch/acpigen.h> +#include <arch/smp/mpspec.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> +#include <cpu/x86/msr.h> #include "dmi.h" +#define OLD_ACPI 0 + extern unsigned char AmlCode[]; +#if HAVE_ACPI_SLIC +unsigned long acpi_create_slic(unsigned long current); +#endif +void generate_cpu_entries(void); // from cpu/intel/speedstep +unsigned long acpi_fill_mcfg(unsigned long current); // from northbridge/intel/i945 +#if OLD_ACPI typedef struct acpi_oemb { acpi_header_t header; u8 ss; @@ -55,13 +67,24 @@ u8 dts2; u8 mpen; } __attribute__((packed)) acpi_oemb_t; +#endif +typedef struct acpi_gnvs { + // 0x00 + u16 osys; + u8 smif; + u8 reserved[13]; + // 0x10 + u8 mpen; +} __attribute__((packed)) acpi_gnvs_t; + +#if OLD_ACPI void acpi_create_oemb(acpi_oemb_t *oemb) { acpi_header_t *header = &(oemb->header); unsigned long tolud; - memset (oemb, 0, sizeof(oemb)); + memset (oemb, 0, sizeof(*oemb)); /* fill out header fields */ memcpy(header->signature, "OEMB", 4); @@ -93,48 +116,12 @@ acpi_checksum((void *) oemb, sizeof(acpi_oemb_t)); }; +#endif -unsigned long acpi_fill_mcfg(unsigned long current) +void acpi_create_gnvs(acpi_gnvs_t *gnvs) { - device_t dev; - u32 pciexbar = 0; - u32 pciexbar_reg; - int max_buses; - - dev = dev_find_device(0x8086, 0x27a0, 0); - if (!dev) - return current; - - // MMCFG not supported or not enabled. - pciexbar_reg=pci_read_config32(dev, 0x48); - - if (!(pciexbar_reg & (1 << 0))) - return current; - - switch ((pciexbar_reg >> 1) & 3) { - case 0: // 256MB - pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)); - max_buses = 256; - break; - case 1: // 128M - pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)); - max_buses = 128; - break; - case 2: // 64M - pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)|(1 << 26)); - max_buses = 64; - break; - default: // RSVD - return current; - } - - if (!pciexbar) - return current; - - current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current, - pciexbar, 0x0, 0x0, max_buses - 1); - - return current; + memset((void *)gnvs, 0, sizeof(*gnvs)); + gnvs->mpen = 1; } void acpi_create_intel_hpet(acpi_hpet_t * hpet) @@ -169,27 +156,32 @@ acpi_checksum((void *) hpet, sizeof(acpi_hpet_t)); } - - #define IO_APIC_ADDR 0xfec00000UL unsigned long acpi_fill_madt(unsigned long current) { - /* Local Apic */ - current += acpi_create_madt_lapic((acpi_madt_lapic_t *) current, 1, 0); - // This one is for the second core... Will it hurt? - current += acpi_create_madt_lapic((acpi_madt_lapic_t *) current, 2, 1); + /* Local APICs */ + current = acpi_create_madt_lapics(current); /* IOAPIC */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2, IO_APIC_ADDR, 0); + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + 2, IO_APIC_ADDR, 0); /* INT_SRC_OVR */ - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 0, 2, 0); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 9, 9, 0x000d); // high/level + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 0, 2, 0); + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH); return current; } +unsigned long acpi_fill_ssdt_generator(unsigned long current, char *oem_table_id) +{ + generate_cpu_entries(); + return (unsigned long) (acpigen_get_current()); +} + unsigned long acpi_fill_slit(unsigned long current) { // Not implemented @@ -202,6 +194,7 @@ return current; } +void smm_setup_structures(void *gnvs, void *tcg, void *smi1); #define ALIGN_CURRENT current = ((current + 0x0f) & -0x10) unsigned long write_acpi_tables(unsigned long start) @@ -210,12 +203,20 @@ int i; acpi_rsdp_t *rsdp; acpi_rsdt_t *rsdt; + acpi_xsdt_t *xsdt; acpi_hpet_t *hpet; acpi_madt_t *madt; acpi_mcfg_t *mcfg; acpi_fadt_t *fadt; acpi_facs_t *facs; +#if HAVE_ACPI_SLIC + acpi_header_t *slic; +#endif +#if OLD_ACPI acpi_oemb_t *oemb; +#endif + acpi_gnvs_t *gnvs; + acpi_header_t *ssdt; acpi_header_t *dsdt; current = start; @@ -232,12 +233,16 @@ rsdt = (acpi_rsdt_t *) current; current += sizeof(acpi_rsdt_t); ALIGN_CURRENT; + xsdt = (acpi_xsdt_t *) current; + current += sizeof(acpi_xsdt_t); + ALIGN_CURRENT; /* clear all table memory */ memset((void *) start, 0, current - start); - acpi_write_rsdp(rsdp, rsdt); + acpi_write_rsdp(rsdp, rsdt, xsdt); acpi_write_rsdt(rsdt); + acpi_write_xsdt(xsdt); /* * We explicitly add these tables later on: @@ -248,7 +253,7 @@ current += sizeof(acpi_hpet_t); ALIGN_CURRENT; acpi_create_intel_hpet(hpet); - acpi_add_table(rsdt, hpet); + acpi_add_table(rsdp, hpet); /* If we want to use HPET Timers Linux wants an MADT */ printk_debug("ACPI: * MADT\n"); @@ -257,21 +262,23 @@ acpi_create_madt(madt); current += madt->header.length; ALIGN_CURRENT; - acpi_add_table(rsdt, madt); + acpi_add_table(rsdp, madt); printk_debug("ACPI: * MCFG\n"); mcfg = (acpi_mcfg_t *) current; acpi_create_mcfg(mcfg); current += mcfg->header.length; ALIGN_CURRENT; - acpi_add_table(rsdt, mcfg); + acpi_add_table(rsdp, mcfg); +#if OLD_ACPI printk_debug("ACPI: * OEMB\n"); oemb=(acpi_oemb_t *)current; current += sizeof(acpi_oemb_t); ALIGN_CURRENT; acpi_create_oemb(oemb); - acpi_add_table(rsdt, oemb); + acpi_add_table(rsdp, oemb); +#endif printk_debug("ACPI: * FACS\n"); facs = (acpi_facs_t *) current; @@ -281,34 +288,69 @@ dsdt = (acpi_header_t *) current; current += ((acpi_header_t *) AmlCode)->length; - ALIGN_CURRENT; memcpy((void *) dsdt, (void *) AmlCode, ((acpi_header_t *) AmlCode)->length); -#if 1 +#if OLD_ACPI for (i=0; i < dsdt->length; i++) { - if (*(u32*)(((u32)dsdt) + i) == 0xC0DEBABE) { + if (*(u32*)(((u32)dsdt) + i) == 0xC0DEBEEF) { printk_debug("ACPI: Patching up DSDT at offset 0x%04x -> 0x%08x\n", i, 0x24 + (u32)oemb); *(u32*)(((u32)dsdt) + i) = 0x24 + (u32)oemb; break; } } +#endif + ALIGN_CURRENT; + + /* Pack GNVS into the ACPI table area */ + for (i=0; i < dsdt->length; i++) { + if (*(u32*)(((u32)dsdt) + i) == 0xC0DEBABE) { + printk_debug("ACPI: Patching up global NVS in DSDT at offset 0x%04x -> 0x%08x\n", i, current); + *(u32*)(((u32)dsdt) + i) = current; // 0x92 bytes + break; + } + } + + /* And fill it */ + acpi_create_gnvs(current); + + current += 0x100; + ALIGN_CURRENT; + + /* And tell SMI about it */ + smm_setup_structures((void *)current, NULL, NULL); + /* We patched up the DSDT, so we need to recalculate the checksum */ dsdt->checksum = 0; dsdt->checksum = acpi_checksum((void *)dsdt, dsdt->length); -#endif printk_debug("ACPI: * DSDT @ %p Length %x\n", dsdt, dsdt->length); +#if HAVE_ACPI_SLIC + printk_debug("ACPI: * SLIC\n"); + slic = (acpi_header_t *)current; + current += acpi_create_slic(current); + ALIGN_CURRENT; + acpi_add_table(rsdp, slic); +#endif + printk_debug("ACPI: * FADT\n"); fadt = (acpi_fadt_t *) current; current += sizeof(acpi_fadt_t); ALIGN_CURRENT; acpi_create_fadt(fadt, facs, dsdt); - acpi_add_table(rsdt, fadt); + acpi_add_table(rsdp, fadt); + + printk_debug("ACPI: * SSDT\n"); + ssdt = (acpi_header_t *)current; + acpi_create_ssdt_generator(ssdt, "COREBOOT"); + current += ssdt->length; + acpi_add_table(rsdp, ssdt); + ALIGN_CURRENT; + printk_debug("current = %lx\n", current); printk_debug("ACPI: * DMI (Linux workaround)\n"); Modified: trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/auto.c 2009-07-21 21:57:11 UTC (rev 4457) +++ trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/auto.c 2009-07-21 21:58:20 UTC (rev 4458) @@ -39,6 +39,12 @@ #include "arch/i386/lib/console.c" #include <cpu/x86/bist.h> +#if CONFIG_USBDEBUG_DIRECT +#define DBGP_DEFAULT 1 +#include "southbridge/intel/i82801gx/i82801gx_usb_debug.c" +#include "pc80/usbdebug_direct_serial.c" +#endif + #include "ram/ramtest.c" #include "southbridge/intel/i82801gx/i82801gx_early_smbus.c" #include "reset.c" @@ -48,7 +54,7 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1) -#include "northbridge/intel/i945/ich7.h" +#include "southbridge/intel/i82801gx/i82801gx.h" static void setup_ich7_gpios(void) { /* TODO: This is highly board specific and should be moved */ @@ -302,6 +308,7 @@ void real_main(unsigned long bist) { + u32 reg32; int boot_mode = 0; if (bist == 0) { @@ -313,6 +320,12 @@ /* Set up the console */ uart_init(); + +#if CONFIG_USBDEBUG_DIRECT + i82801gx_enable_usbdebug_direct(DBGP_DEFAULT); + early_usbdebug_direct_init(); +#endif + console_init(); /* Halt if there was a built in self test failure */ @@ -328,6 +341,22 @@ */ i945_early_initialization(); + /* Read PM1_CNT */ + reg32 = inl(DEFAULT_PMBASE + 0x04); + printk_debug("PM1_CNT: %08x\n", reg32); + if (((reg32 >> 10) & 7) == 5) { +#if HAVE_ACPI_RESUME + printk_debug("Resume from S3 detected.\n"); + boot_mode = 2; + /* Clear SLP_TYPE. This will break stage2 but + * we care for that when we get there. + */ + outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04); +#else + printk_debug("Resume from S3 detected, but disabled.\n"); +#endif + } + /* Enable SPD ROMs and DDR-II DRAM */ enable_smbus(); Modified: trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/cmos.layout 2009-07-21 21:57:11 UTC (rev 4457) +++ trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/cmos.layout 2009-07-21 21:58:20 UTC (rev 4458) @@ -86,8 +86,8 @@ # coreboot config options: southbridge 408 1 e 1 nmi -409 1 e 1 power_on_after_fail -#410 6 r 0 unused +409 2 e 7 power_on_after_fail +#411 5 r 0 unused # coreboot config options: bootloader 416 512 s 0 boot_devices @@ -97,6 +97,13 @@ 984 16 h 0 check_sum #1000 24 r 0 amd_reserved +# ram initialization internal data +1024 8 r 0 C0WL0REOST +1032 8 r 0 C1WL0REOST +1040 8 r 0 RCVENMT +1048 4 r 0 C0DRT1 +1052 4 r 0 C1DRT1 + # ----------------------------------------------------------------- enumerations @@ -125,6 +132,9 @@ 6 7 Info 6 8 Debug 6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep # ----------------------------------------------------------------- checksums Modified: trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/dsdt.asl =================================================================== --- trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/dsdt.asl 2009-07-21 21:57:11 UTC (rev 4457) +++ trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/dsdt.asl 2009-07-21 21:58:20 UTC (rev 4458) @@ -25,21 +25,18 @@ 0x02, // DSDT revision: ACPI v2.0 "COREv2", // OEM id "COREBOOT", // OEM table id - 0x00000001 // OEM revision + 0x20090419 // OEM revision ) { // Some generic macros Include ("acpi/platform.asl") // global NVS and variables - Include ("acpi/globalnvs.asl") + Include ("../../../southbridge/intel/i82801gx/acpi/globalnvs.asl") // General Purpose Events //include ("acpi/gpe.asl") - /* CPU node(s) */ - include ("acpi/cpu.asl") - //include ("acpi/thermal.asl") Scope (\_SB) { @@ -50,6 +47,6 @@ } } - /* Board and Chipset specific sleep states */ - include ("acpi/sleepstates.asl") + /* Chipset specific sleep states */ + include ("../../../southbridge/intel/i82801gx/acpi/sleepstates.asl") } Modified: trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/fadt.c =================================================================== --- trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/fadt.c 2009-07-21 21:57:11 UTC (rev 4457) +++ trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/fadt.c 2009-07-21 21:58:20 UTC (rev 4458) @@ -23,6 +23,17 @@ #include <device/pci.h> #include <arch/acpi.h> +/* FIXME: This needs to go into a separate .h file + * to be included by the ich7 smi handler, ich7 smi init + * code and the mainboard fadt. + */ +#define APM_CNT 0xb2 +#define CST_CONTROL 0x00 // 0xe3 crashes the box +#define PST_CONTROL 0x00 // 0xe2 crashes the box +#define ACPI_DISABLE 0x1e +#define ACPI_ENABLE 0xe1 +#define GNVS_UPDATE 0xea + void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) { acpi_header_t *header = &(fadt->header); @@ -30,8 +41,8 @@ memset((void *) fadt, 0, sizeof(acpi_fadt_t)); memcpy(header->signature, "FACP", 4); - header->length = 132; - header->revision = 2; + header->length = sizeof(acpi_fadt_t); + header->revision = 3; memcpy(header->oem_id, "CORE ", 6); memcpy(header->oem_table_id, "COREBOOT", 8); memcpy(header->asl_compiler_id, "CORE", 4); @@ -40,14 +51,15 @@ fadt->firmware_ctrl = (unsigned long) facs; fadt->dsdt = (unsigned long) dsdt; fadt->model = 1; - fadt->preferred_pm_profile = 2; - fadt->sci_int = 0x9; - fadt->smi_cmd = 0xb2; - fadt->acpi_enable = 0xe1; - fadt->acpi_disable = 0x1e; - fadt->s4bios_req = 0x0; - fadt->pstate_cnt = 0xe2; + fadt->preferred_pm_profile = PM_MOBILE; + fadt->sci_int = 0x9; + fadt->smi_cmd = APM_CNT; + fadt->acpi_enable = ACPI_ENABLE; + fadt->acpi_disable = ACPI_DISABLE; + fadt->s4bios_req = 0x0; + fadt->pstate_cnt = PST_CONTROL; + fadt->pm1a_evt_blk = pmbase; fadt->pm1b_evt_blk = 0x0; fadt->pm1a_cnt_blk = pmbase + 0x4; @@ -59,12 +71,13 @@ fadt->pm1_evt_len = 4; fadt->pm1_cnt_len = 2; - fadt->pm2_cnt_len = 0; + // XXX: pm2_cnt_len is probably wrong. find out right value (hint: it's != 0) + fadt->pm2_cnt_len = 2; fadt->pm_tmr_len = 4; fadt->gpe0_blk_len = 8; fadt->gpe1_blk_len = 0; fadt->gpe1_base = 0; - fadt->cst_cnt = 0xe3; + fadt->cst_cnt = CST_CONTROL; fadt->p_lvl2_lat = 1; fadt->p_lvl3_lat = 85; fadt->flush_size = 1024; @@ -75,14 +88,80 @@ fadt->mon_alrm = 0x00; fadt->century = 0x00; fadt->iapc_boot_arch = 0x03; - fadt->flags = 0x80a5; - // wbinvd is operational - // all cpus support c1 - // sleep button is generic - // rtc wakeup/s4 not possible - // use platform timer - + + fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | + ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | + ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; + + fadt->reset_reg.space_id = 0; + fadt->reset_reg.bit_width = 0; + fadt->reset_reg.bit_offset = 0; + fadt->reset_reg.resv = 0; + fadt->reset_reg.addrl = 0x0; + fadt->reset_reg.addrh = 0x0; + + fadt->reset_value = 0; + fadt->x_firmware_ctl_l = (unsigned long)facs; + fadt->x_firmware_ctl_h = 0; + fadt->x_dsdt_l = (unsigned long)dsdt; + fadt->x_dsdt_h = 0; + + fadt->x_pm1a_evt_blk.space_id = 1; + fadt->x_pm1a_evt_blk.bit_width = 32; + fadt->x_pm1a_evt_blk.bit_offset = 0; + fadt->x_pm1a_evt_blk.resv = 0; + fadt->x_pm1a_evt_blk.addrl = pmbase; + fadt->x_pm1a_evt_blk.addrh = 0x0; + + fadt->x_pm1b_evt_blk.space_id = 1; + fadt->x_pm1b_evt_blk.bit_width = 0; + fadt->x_pm1b_evt_blk.bit_offset = 0; + fadt->x_pm1b_evt_blk.resv = 0; + fadt->x_pm1b_evt_blk.addrl = 0x0; + fadt->x_pm1b_evt_blk.addrh = 0x0; + + fadt->x_pm1a_cnt_blk.space_id = 1; + fadt->x_pm1a_cnt_blk.bit_width = 16; + fadt->x_pm1a_cnt_blk.bit_offset = 0; + fadt->x_pm1a_cnt_blk.resv = 0; + fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; + fadt->x_pm1a_cnt_blk.addrh = 0x0; + + fadt->x_pm1b_cnt_blk.space_id = 1; + fadt->x_pm1b_cnt_blk.bit_width = 0; + fadt->x_pm1b_cnt_blk.bit_offset = 0; + fadt->x_pm1b_cnt_blk.resv = 0; + fadt->x_pm1b_cnt_blk.addrl = 0x0; + fadt->x_pm1b_cnt_blk.addrh = 0x0; + + fadt->x_pm2_cnt_blk.space_id = 1; + fadt->x_pm2_cnt_blk.bit_width = 8; + fadt->x_pm2_cnt_blk.bit_offset = 0; + fadt->x_pm2_cnt_blk.resv = 0; + fadt->x_pm2_cnt_blk.addrl = pmbase + 0x20; + fadt->x_pm2_cnt_blk.addrh = 0x0; + + fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.bit_width = 32; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.resv = 0; + fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; + fadt->x_pm_tmr_blk.addrh = 0x0; + + fadt->x_gpe0_blk.space_id = 1; + fadt->x_gpe0_blk.bit_width = 64; + fadt->x_gpe0_blk.bit_offset = 0; + fadt->x_gpe0_blk.resv = 0; + fadt->x_gpe0_blk.addrl = pmbase + 0x28; + fadt->x_gpe0_blk.addrh = 0x0; + + fadt->x_gpe1_blk.space_id = 1; + fadt->x_gpe1_blk.bit_width = 0; + fadt->x_gpe1_blk.bit_offset = 0; + fadt->x_gpe1_blk.resv = 0; + fadt->x_gpe1_blk.addrl = 0x0; + fadt->x_gpe1_blk.addrh = 0x0; + header->checksum = acpi_checksum((void *) fadt, header->length); - } Modified: trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/mainboard.c =================================================================== --- trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/mainboard.c 2009-07-21 21:57:11 UTC (rev 4457) +++ trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/mainboard.c 2009-07-21 21:58:20 UTC (rev 4458) @@ -25,16 +25,11 @@ #include <boot/tables.h> #include "chip.h" -/* in northbridge/intel/i945/northbridge.c */ -extern uint64_t uma_memory_base, uma_memory_size; +int add_northbridge_resources(struct lb_memory *mem); int add_mainboard_resources(struct lb_memory *mem) { - printk_debug("Adding UMA memory area\n"); - lb_add_memory_range(mem, LB_MEM_RESERVED, - uma_memory_base, uma_memory_size); - - return 0; + return add_northbridge_resources(mem); } struct chip_operations mainboard_ops = { Modified: trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/mainboard_smi.c =================================================================== --- trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/mainboard_smi.c 2009-07-21 21:57:11 UTC (rev 4457) +++ trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/mainboard_smi.c 2009-07-21 21:58:20 UTC (rev 4458) @@ -24,10 +24,13 @@ #include <console/console.h> #include "../../../southbridge/intel/i82801gx/i82801gx_nvs.h" +/* The southbridge SMI handler checks whether gnvs has a + * valid pointer before calling the trap handler + */ +extern global_nvs_t *gnvs; + int mainboard_io_trap_handler(int smif) { - global_nvs_t *gnvs = (global_nvs_t *)0xc00; - switch (smif) { case 0x99: printk_debug("Sample\n"); -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
