[coreboot] [PATCH]:The Errata350 is fixed as the way it should be

[Bao, Zheng]

The Errata350 is "Write 0000_8000h to register F2x[1, 0]9C_xD080F0C.",
instead of
F2x[1, 0]9C_x0C. It is a obvious bug. Some typos are also fixed.


Index: src/northbridge/amd/amdmct/wrappers/mcti_d.c
===================================================================
--- src/northbridge/amd/amdmct/wrappers/mcti_d.c        (revision 4521)
+++ src/northbridge/amd/amdmct/wrappers/mcti_d.c        (working copy)
@@ -347,45 +347,45 @@
                        u32Addr = mct_GetRcvrSysAddr_D(pMCTstat,
pDCTstat, u8Channel, u8Receiver, &u8Valid);
 
                        if(!u8Valid) {  /* Address not supported on
current CS */
-                               print_t("vErrara350: Address not
supported on current CS\n");
+                               print_t("vErrata350: Address not
supported on current CS\n");
                                continue;
                        }
-                       print_t("vErrara350: dummy read \n");
+                       print_t("vErrata350: dummy read \n");
                        read32_fs(u32Addr);
                }
        }
 
-       print_t("vErrara350: step 2a\n");
+       print_t("vErrata350: step 2a\n");
 
        /* 2. Write 0000_8000h to register F2x[1, 0]9C_xD080F0C. */
        u32DctDev = pDCTstat->dev_dct;
-       Set_NB32_index_wait(u32DctDev, 0x098, 0x0c, 0x00008000);
+       Set_NB32_index_wait(u32DctDev, 0x098, 0xD080F0C, 0x00008000);
        /*                                                ^--- value
-                                               ^---F2x[1, 0]9C_x0C DRAM
Phy Miscellaneous Register
+                                               ^---F2x[1,
0]9C_x0D080F0C, No description in BKDG.
                                         ^----F2x[1, 0]98 DRAM
Controller Additional Data Offset Register */
 
        if(!pDCTstat->GangedMode) {
-               print_t("vErrara350: step 2b\n");
-               Set_NB32_index_wait(u32DctDev, 0x198, 0x0c, 0x00008000);
+               print_t("vErrata350: step 2b\n");
+               Set_NB32_index_wait(u32DctDev, 0x198, 0xD080F0C,
0x00008000);
                /*                                                ^---
value
-                                                       ^---F2x[1,
0]9C_x0C DRAM Phy Miscellaneous Register
+                                                       ^---F2x[1,
0]9C_x0D080F0C, No description in BKDG
                                                ^----F2x[1, 0]98 DRAM
Controller Additional Data Offset Register */
        }
 
-       print_t("vErrara350: step 3\n");
+       print_t("vErrata350: step 3\n");
        /* 3. Wait at least 300 nanoseconds. */
        coreDelay();
 
-       print_t("vErrara350: step 4\n");
+       print_t("vErrata350: step 4\n");
        /* 4. Write 0000_0000h to register F2x[1, 0]9C_xD080F0C. */
-       Set_NB32_index_wait(u32DctDev, 0x098, 0x0c, 0x00000000);
+       Set_NB32_index_wait(u32DctDev, 0x098, 0xD080F0C, 0x00000000);
 
        if(!pDCTstat->GangedMode) {
-               print_t("vErrara350: step 4b\n");
-               Set_NB32_index_wait(u32DctDev, 0x198, 0x0c, 0x00000000);
+               print_t("vErrata350: step 4b\n");
+               Set_NB32_index_wait(u32DctDev, 0x198, 0xD080F0C,
0x00000000);
        }
 
-       print_t("vErrara350: step 5\n");
+       print_t("vErrata350: step 5\n");
        /* 5. Wait at least 2 microseconds. */
        coreDelay();

fix_fam10_Errata350.patch
Description: fix_fam10_Errata350.patch

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