Index: mainboard/via/epia-n/Options.lb
===================================================================
--- mainboard/via/epia-n/Options.lb	(revision 4553)
+++ mainboard/via/epia-n/Options.lb	(working copy)
@@ -96,9 +96,7 @@
 default CONFIG_IRQ_SLOT_COUNT = 7
 default CONFIG_HAVE_ACPI_TABLES = 1
 default CONFIG_HAVE_OPTION_TABLE = 1
-#default CONFIG_ROM_IMAGE_SIZE = 67 * 1024
-#default CONFIG_PAYLOAD_SIZE = 125 * 1024
-default CONFIG_ROM_IMAGE_SIZE = 128 * 1024
+default CONFIG_ROM_IMAGE_SIZE = 67 * 1024
 default CONFIG_PAYLOAD_SIZE = 256 * 1024
 default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
 default CONFIG_USE_FALLBACK_IMAGE = 1
Index: northbridge/via/cn400/agp.c
===================================================================
--- northbridge/via/cn400/agp.c	(revision 4553)
+++ northbridge/via/cn400/agp.c	(working copy)
@@ -144,22 +144,7 @@
 
 static void agp_bridge_read_resources (device_t dev)
 {
-	struct resource *res;
-
-	res = new_resource(dev, 1);
-	res->base = 0xF0000000ULL;
-	res->size = 0x06000000ULL;
-	res->limit = 0xffffffffULL;
-	res->flags = IORESOURCE_MEM | IORESOURCE_FIXED |
-		     		IORESOURCE_STORED | IORESOURCE_ASSIGNED;
-
-	res = new_resource(dev, 2);
-	res->base = 0xB000UL;
-	res->size = 4096;
-	res->limit = 0xffffUL;
-	res->flags = IORESOURCE_IO | IORESOURCE_FIXED |
-		     		IORESOURCE_STORED | IORESOURCE_ASSIGNED;
-
+	return;
 }
 /*
  * This is the AGP 3.0 "bridge" @Bus 0 Device 1 Func 0. When using AGP 3.0, the
@@ -208,6 +193,7 @@
 	pci_write_config8(dev, 0x44, 0x34);
 	pci_write_config8(dev, 0x45, 0x72);
 
+#ifdef DEBUG_CN400
 	printk_spew("%s PCI Header Regs::\n", dev_path(dev));
 
 	for (i = 0 ; i < 16; i++)
@@ -221,6 +207,7 @@
 		printk_spew("\n");
 	}
 
+#endif
 }
 
 static const struct device_operations agp_bridge_operations = {
Index: northbridge/via/cn400/cn400.h
===================================================================
--- northbridge/via/cn400/cn400.h	(revision 4553)
+++ northbridge/via/cn400/cn400.h	(working copy)
@@ -24,7 +24,7 @@
 }
 #endif
 
-#define DEBUG_CN400
+//#define DEBUG_CN400
 
 /* VGA stuff */
 #define SR_INDEX		0x3c4
Index: northbridge/via/cn400/vgabios.c
===================================================================
--- northbridge/via/cn400/vgabios.c	(revision 4553)
+++ northbridge/via/cn400/vgabios.c	(working copy)
@@ -2,6 +2,7 @@
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <device/pci_ops.h>
+#include <cbfs.h>
 #undef __KERNEL__
 #include <arch/io.h>
 //#include <printk.h>
@@ -356,13 +357,19 @@
 	/* declare rom address here - keep any config data out of the way
 	 * of core LXB stuff */
 
-	rom = 0xfff80000;
+	struct cbfs_optionrom *vga_rom = cbfs_find_file("pci1106,3118.rom", CBFS_TYPE_OPTIONROM);
+	if (vga_rom == NULL)
+	{
+		printk_info("ERROR: Could not locate VGA Option ROM\n");
+		return;
+	}
+	buf = (unsigned char *) vga_rom;
+	rom = (unsigned int) buf;
 	pci_write_config32(dev, PCI_ROM_ADDRESS, rom|1);
 	printk_debug("VGA BIOS ROM base address: %x\n", rom);
 
-	buf = (unsigned char *) rom;
 	if ((buf[0] == 0x55) && (buf[1] == 0xaa)) {
-		memcpy((void *) 0xc0000, buf, size);
+		memcpy((void *) 0xc0000, (unsigned char *)buf, size);
 
 		write_protect_vgabios();  // in northbridge
 
Index: northbridge/via/cn400/vga.c
===================================================================
--- northbridge/via/cn400/vga.c	(revision 4553)
+++ northbridge/via/cn400/vga.c	(working copy)
@@ -33,6 +33,7 @@
 #include <string.h>
 #include <bitops.h>
 #include <cpu/cpu.h>
+#include <cbfs.h>
 #include "chip.h"
 #include "northbridge.h"
 #include "cn400.h"
@@ -46,19 +47,24 @@
 static void vga_init(device_t dev)
 {
 	u8 reg8;
-	u32 temp;
 #ifdef DEBUG_CN400
 	int i, j;
 #endif
 
-	temp = (0xffffffff - CONFIG_FALLBACK_SIZE - 0xffff);
-	printk_debug("Copying BOCHS BIOS from 0x%08X	to 0xf000\n", temp);
+	printk_debug("Copying BOCHS BIOS to 0xf0000\n");
 	/*
 	 * Copy BOCHS BIOS from 4G-CONFIG_FALLBACK_SIZE-64k (in flash) to 0xf0000 (in RAM)
 	 * This is for compatibility with the VGA ROM's BIOS callbacks.
 	 */
-	//memcpy(0xf0000, (0xffffffff - CONFIG_ROM_SIZE - 0xffff), 0x10000);
-	memcpy(0xf0000, temp, 0x10000);
+	struct cbfs_optionrom *bochs = cbfs_find_file("pciffff,e91a.rom", CBFS_TYPE_OPTIONROM);
+	if (bochs == NULL)
+	{
+		printk_info("ERROR: Could not locate BOCHS ROM File\n");
+		return;
+	}
+	printk_debug("Located BOCHS option ROM at 0x%08X\n", (u32) bochs);
+	memcpy(0xf0000, (unsigned char *)bochs, 0x10000);
+
 	printk_debug("Initializing VGA\n");
 
 	/* Set memory rate to 200 MHz. */
@@ -123,9 +129,24 @@
 
 static void vga_read_resources(device_t dev)
 {
+	struct resource *res;
+
 	dev->rom_address = 0xfff80000;
 	dev->on_mainboard = 1;
 	pci_dev_read_resources(dev);
+
+	res = new_resource(dev, 0x10);
+	res->base = 0xF0000000ULL;
+	res->size = 0x04000000ULL;
+	res->limit = 0xffffffffULL;
+	res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH | 
+					IORESOURCE_FIXED | IORESOURCE_ASSIGNED;
+
+	res = new_resource(dev, 0x14);
+	res->base = 0xF4000000ULL;
+	res->size = 0x01000000ULL;
+	res->limit = 0xffffffffULL;
+	res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_ASSIGNED;
 }
 
 static const struct device_operations vga_operations = {