---------- Forwarded message ----------
From: Daniel Toussaint <[email protected]>
Date: Fri, Aug 21, 2009 at 2:33 PM
Subject: Re: [coreboot] AMD RS690 TMDS
To: Karl-Heinz Nirschl <[email protected]>
Hello,
Meanwhile one of my team members has solved the problem, the info was all in
the BIOS porting guide, it was just not very obvious. Below is his patch:
Enable Direct TMDS for the RS690, which allows to display on HDMI and DVI
monitors.
Signed-off-by: Libra Li <[email protected]>
On Tue, Aug 18, 2009 at 2:33 AM, Karl-Heinz Nirschl <
[email protected]> wrote:
> hi,
>
> i have a m2a-vm hdmi and could provide dumps if needed. just tell me
> exactly what you need.
>
> best regards
>
> khn
>
> 2009/8/17 Carl-Daniel Hailfinger <[email protected]>:
> > Hi Daniel,
> >
> > On 11.08.2009 18:32, Daniel Toussaint wrote:
> >> I am using the open source drivers , radeon and radeonhd. When I try it
> on a
> >> similar board with AMI bios , xrandr can switch on the HDMI port without
> any
> >> problems - with radeon and radeonhd. I guess I could give Catalyst a try
> to
> >> see if it makes any difference(maybe it does magic with the vga bios) I
> >> think however, that the problem lies in the fact that some config needs
> to
> >> be done in PCIE-GFX , so that one of the ports gets configured as TMDS.
> >> Right now, I am trying to get that to work - so far no results yet ....
> >> Another interesting fact is that I am working with this board that does
> not
> >> have another BIOS except for coreboot .... so I have nothing to compare
> >> register values with.
> >>
> >
> > I never tested HDMI on my board and I know that most boards need special
> > PCIe setup to get HDMI working. So unless this is implemented already,
> > you probably need to code it up yourself.
> > The issue should be independent of the video driver you're using.
> >
> > Maybe someone who has a board with working HDMI under the proprietary
> > BIOS can give you the register dumps you need.
> >
> > Regards,
> > Carl-Daniel
> >
> > --
> > http://www.hailfinger.org/
> >
> >
> > --
> > coreboot mailing list: [email protected]
> > http://www.coreboot.org/mailman/listinfo/coreboot
> >
>
Index: src/southbridge/amd/rs690/rs690_pcie.c
===================================================================
--- src/southbridge/amd/rs690/rs690_pcie.c (revision 4559)
+++ src/southbridge/amd/rs690/rs690_pcie.c (working copy)
@@ -87,18 +87,21 @@
Config & (PCIE_DISABLE_HIDE_UNUSED_PORTS +
PCIE_GFX_COMPLIANCE))) {
}
- /* step 3 Power Down Control for Southbridge */
- reg = nbpcie_p_read_index(dev, 0xa2);
- switch ((reg >> 4) & 0x7) { /* get bit 4-6, LC_LINK_WIDTH_RD */
- case 1:
- nbpcie_ind_write_index(nb_dev, 0x65, 0x0e0e);
- break;
- case 2:
- nbpcie_ind_write_index(nb_dev, 0x65, 0x0c0c);
- break;
- default:
- break;
+ if (!cfg->gfx_tmds){
+ /* step 3 Power Down Control for Southbridge */
+ reg = nbpcie_p_read_index(dev, 0xa2);
+
+ switch ((reg >> 4) & 0x7) { /* get bit 4-6, LC_LINK_WIDTH_RD */
+ case 1:
+ nbpcie_ind_write_index(nb_dev, 0x65, 0x0e0e);
+ break;
+ case 2:
+ nbpcie_ind_write_index(nb_dev, 0x65, 0x0c0c);
+ break;
+ default:
+ break;
+ }
}
}
Index: src/southbridge/amd/rs690/rs690_gfx.c
===================================================================
--- src/southbridge/amd/rs690/rs690_gfx.c (revision 4559)
+++ src/southbridge/amd/rs690/rs690_gfx.c (working copy)
@@ -471,7 +471,49 @@
/* done by enable_pci_bar3() before */
/* step 6 SBIOS compile flags */
+ if (cfg->gfx_tmds) {
+ /* step 6.2.2 Clock-Muxing Control */
+ /* step 6.2.2.1 */
+ set_nbmisc_enable_bits(nb_dev, 0x7, 1 << 16, 1 << 16);
+ /* step 6.2.2.2 */
+ set_nbmisc_enable_bits(nb_dev, 0x7, 1 << 8, 1 << 8);
+ set_nbmisc_enable_bits(nb_dev, 0x7, 1 << 10, 1 << 10);
+
+ /* step 6.2.2.3 */
+ set_nbmisc_enable_bits(nb_dev, 0x7, 1 << 26, 1 << 26);
+
+ /* step 6.2.3 Lane-Muxing Control */
+ /* step 6.2.3.1 */
+ set_nbmisc_enable_bits(nb_dev, 0x37, 0x3 << 8, 0x2 << 8);
+
+ /* step 6.2.4 Received Data Control */
+ /* step 6.2.4.1 */
+ set_pcie_enable_bits(nb_dev, 0x40, 0x3 << 16, 0x2 << 16);
+
+ /* step 6.2.4.2 */
+ set_pcie_enable_bits(nb_dev, 0x40, 0x3 << 18, 0x3 << 18);
+
+ /* step 6.2.4.3 */
+ set_pcie_enable_bits(nb_dev, 0x40, 0x3 << 20, 0x0 << 20);
+
+ /* step 6.2.4.4 */
+ set_pcie_enable_bits(nb_dev, 0x40, 0x3 << 22, 0x1 << 22);
+
+ /* step 6.2.5 PLL Power Down Control */
+ /* step 6.2.5.1 */
+ set_nbmisc_enable_bits(nb_dev, 0x35, 0x3 << 6, 0x0 << 6);
+
+ /* step 6.2.6 Driving Strength Control */
+ /* step 6.2.6.1 */
+ set_nbmisc_enable_bits(nb_dev, 0x34, 0x1 << 24, 0x0 << 24);
+
+ /* step 6.2.6.2 */
+ set_nbmisc_enable_bits(nb_dev, 0x35, 0x3 << 2, 0x3 << 2);
+ }
+
+ printk_info("rs690_gfx_init step6.\n");
+
/* step 7 compliance state, (only need if CMOS option is enabled) */
/* the compliance stete is just for test. refer to 4.2.5.2 of PCIe specification */
if (cfg->gfx_compliance) {
--
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