Peter Stuge wrote: > Stefan Reinauer wrote: > >>> coreboot does support this since a few years already. >>> >> On some chipsets... There is a certain amount of (non-trivial) >> chipset specific setup. >> > > What's that? > > EHCI is always the same, but is there stuff to do so the EHC is > reachable? >
I have not figured it out yet. Our code is not working on Intel ICH, however. Grep the southbridge directories for usbdebug... Stefan -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
