Author: myles Date: 2009-09-22 20:53:50 +0200 (Tue, 22 Sep 2009) New Revision: 4656
Added: trunk/coreboot-v2/src/mainboard/tyan/Makefile.s289x.inc trunk/coreboot-v2/src/mainboard/tyan/s2891/Kconfig trunk/coreboot-v2/src/mainboard/tyan/s2891/Makefile.inc trunk/coreboot-v2/src/mainboard/tyan/s2892/Kconfig trunk/coreboot-v2/src/mainboard/tyan/s2892/Makefile.inc trunk/coreboot-v2/src/mainboard/tyan/s2895/Kconfig trunk/coreboot-v2/src/mainboard/tyan/s2895/Makefile.inc Modified: trunk/coreboot-v2/src/mainboard/tyan/Kconfig trunk/coreboot-v2/src/mainboard/tyan/s2895/Config.lb trunk/coreboot-v2/src/mainboard/tyan/s2895/cache_as_ram_auto.c trunk/coreboot-v2/src/southbridge/nvidia/ck804/Kconfig trunk/coreboot-v2/targets/tyan/s2895/Config-abuild.lb trunk/coreboot-v2/targets/tyan/s2895/Config.lb Log: failoverR.diff: Revert my failover change since Kconfig only supports fallback. kconfig_s2892.dif: Add support for Tyan s2891, s2892, and s2895 to Kconfig. Signed-off-by: Myles Watson <[email protected]> Acked-by: Ronald G. Minnich <[email protected]> Modified: trunk/coreboot-v2/src/mainboard/tyan/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/Kconfig 2009-09-22 18:49:08 UTC (rev 4655) +++ trunk/coreboot-v2/src/mainboard/tyan/Kconfig 2009-09-22 18:53:50 UTC (rev 4656) @@ -23,6 +23,9 @@ depends on VENDOR_TYAN source "src/mainboard/tyan/s1846/Kconfig" +source "src/mainboard/tyan/s2891/Kconfig" +source "src/mainboard/tyan/s2892/Kconfig" +source "src/mainboard/tyan/s2895/Kconfig" endchoice Copied: trunk/coreboot-v2/src/mainboard/tyan/Makefile.s289x.inc (from rev 4611, trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Makefile.inc) =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/Makefile.s289x.inc (rev 0) +++ trunk/coreboot-v2/src/mainboard/tyan/Makefile.s289x.inc 2009-09-22 18:53:50 UTC (rev 4656) @@ -0,0 +1,73 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## +## This program is free software; you can redistribute it and/or +## modify it under the terms of the GNU General Public License as +## published by the Free Software Foundation; version 2 of +## the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +## MA 02110-1301 USA +## + +## +## This mainboard requires DCACHE_AS_RAM enabled. It won't work without. +## + +driver-y += mainboard.o + +#needed by irq_tables and mptable and acpi_tables +obj-y += get_bus_conf.o +obj-$(CONFIG_HAVE_MP_TABLE) += mptable.o +obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o +obj-$(CONFIG_HAVE_ACPI_TABLES) += dsdt.o +obj-$(CONFIG_HAVE_ACPI_TABLES) += acpi_tables.o + +#driver-y += ../../../drivers/i2c/i2cmux/i2cmux.o + +# This is part of the conversion to init-obj and away from included code. + +initobj-y += crt0.o +# FIXME in $(top)/Makefile +crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc +crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc +crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc +crt0-y += ../../../../src/southbridge/nvidia/ck804/id.inc +crt0-y += ../../../../src/southbridge/nvidia/ck804/romstrap.inc +crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc +crt0-y += auto.inc + +ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb +ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds +ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds +ldscript-y += ../../../../src/southbridge/nvidia/ck804/id.lds +ldscript-y += ../../../../src/southbridge/nvidia/ck804/romstrap.lds +ldscript-y += ../../../../src/arch/i386/lib/failover.lds + +ifdef POST_EVALUATION + +MAINBOARD_OPTIONS= -DCONFIG_AP_IN_SIPI_WAIT=0 + +$(obj)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/dsdt.dsl + iasl -p dsdt -tc $(src)/mainboard/$(MAINBOARDDIR)/dsdt.dsl + mv dsdt.hex $@ + +$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c + $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@ + +$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c $(obj)/option_table.h + $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c -o $@ + perl -e 's/\.rodata/.rom.data/g' -pi $@ + perl -e 's/\.text/.section .rom.text/g' -pi $@ + +endif + Property changes on: trunk/coreboot-v2/src/mainboard/tyan/Makefile.s289x.inc ___________________________________________________________________ Added: svn:mergeinfo + Copied: trunk/coreboot-v2/src/mainboard/tyan/s2891/Kconfig (from rev 4611, trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Kconfig) =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2891/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/tyan/s2891/Kconfig 2009-09-22 18:53:50 UTC (rev 4656) @@ -0,0 +1,142 @@ +config BOARD_TYAN_S2891 + bool "Tyan Thunder K8SRE S2891" + select ARCH_X86 + select CPU_AMD_K8 + select CPU_AMD_SOCKET_940 + select NORTHBRIDGE_AMD_AMDK8 + select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX + select SOUTHBRIDGE_NVIDIA_CK804 + select SOUTHBRIDGE_AMD_AMD8131 + select SUPERIO_WINBOND_W83627HF + select PIRQ_TABLE + +config MAINBOARD_DIR + string + default tyan/s2891 + depends on BOARD_TYAN_S2891 + +config APIC_ID_OFFSET + hex + default 8 + depends on BOARD_TYAN_S2891 + +config SB_HT_CHAIN_ON_BUS0 + int + default 2 + depends on BOARD_TYAN_S2891 + +config LB_CKS_RANGE_END + int + default 122 + depends on BOARD_TYAN_S2891 + +config LB_CKS_LOC + int + default 123 + depends on BOARD_TYAN_S2891 + +config MAINBOARD_PART_NUMBER + string + default "s2891" + depends on BOARD_TYAN_S2891 + +config CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID + hex + default 0x2891 + depends on BOARD_TYAN_S2891 + +config USE_FAILOVER_IMAGE + bool + default n + depends on BOARD_TYAN_S2891 + +config HW_MEM_HOLE_SIZEK + hex + default 0x100000 + depends on BOARD_TYAN_S2891 + +config MEM_TRAIN_SEQ + bool + default n + depends on BOARD_TYAN_S2891 + +config HAVE_FAILOVER_BOOT + bool + default n + depends on BOARD_TYAN_S2891 + +config USE_FAILOVER_IMAGE + bool + default n + depends on BOARD_TYAN_S2891 + +config MAX_CPUS + int + default 4 + depends on BOARD_TYAN_S2891 + +config MAX_PHYSICAL_CPUS + int + default 2 + depends on BOARD_TYAN_S2891 + +config MEM_TRAIN_SEQ + bool + default n + depends on BOARD_TYAN_S2891 + +config AP_CODE_IN_CAR + bool + default n + depends on BOARD_TYAN_S2891 + +config HW_MEM_HOLE_SIZE_AUTO_INC + bool + default n + depends on BOARD_TYAN_S2891 + +config HT_CHAIN_UNITID_BASE + hex + default 0 + depends on BOARD_TYAN_S2891 + +config HT_CHAIN_END_UNITID_BASE + hex + default 0x20 + depends on BOARD_TYAN_S2891 + +config USE_INIT + bool + default n + depends on BOARD_TYAN_S2891 + +config SERIAL_CPU_INIT + bool + default y + depends on BOARD_TYAN_S2891 + +config AP_CODE_IN_CAR + bool + default y + depends on BOARD_TYAN_S2891 + +config WAIT_BEFORE_CPUS_INIT + bool + default n + depends on BOARD_TYAN_S2891 + +config SB_HT_CHAIN_ON_BUS0 + int + default 2 + depends on BOARD_TYAN_S2891 + +config SB_HT_CHAIN_UNITID_OFFSET_ONLY + bool + default n + depends on BOARD_TYAN_S2891 + +config HAVE_ACPI_TABLES + bool "Generate ACPI tables" + default y + depends on BOARD_TYAN_S2891 + Property changes on: trunk/coreboot-v2/src/mainboard/tyan/s2891/Kconfig ___________________________________________________________________ Added: svn:mergeinfo + Added: trunk/coreboot-v2/src/mainboard/tyan/s2891/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2891/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/mainboard/tyan/s2891/Makefile.inc 2009-09-22 18:53:50 UTC (rev 4656) @@ -0,0 +1 @@ +include $(src)/mainboard/tyan/Makefile.s289x.inc Copied: trunk/coreboot-v2/src/mainboard/tyan/s2892/Kconfig (from rev 4611, trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Kconfig) =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2892/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/tyan/s2892/Kconfig 2009-09-22 18:53:50 UTC (rev 4656) @@ -0,0 +1,142 @@ +config BOARD_TYAN_S2892 + bool "Tyan Thunder K8SE S2892" + select ARCH_X86 + select CPU_AMD_K8 + select CPU_AMD_SOCKET_940 + select NORTHBRIDGE_AMD_AMDK8 + select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX + select SOUTHBRIDGE_NVIDIA_CK804 + select SOUTHBRIDGE_AMD_AMD8131 + select SUPERIO_WINBOND_W83627HF + select PIRQ_TABLE + +config MAINBOARD_DIR + string + default tyan/s2892 + depends on BOARD_TYAN_S2892 + +config APIC_ID_OFFSET + hex + default 8 + depends on BOARD_TYAN_S2892 + +config SB_HT_CHAIN_ON_BUS0 + int + default 2 + depends on BOARD_TYAN_S2892 + +config LB_CKS_RANGE_END + int + default 122 + depends on BOARD_TYAN_S2892 + +config LB_CKS_LOC + int + default 123 + depends on BOARD_TYAN_S2892 + +config MAINBOARD_PART_NUMBER + string + default "s2892" + depends on BOARD_TYAN_S2892 + +config CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID + hex + default 0x2892 + depends on BOARD_TYAN_S2892 + +config USE_FAILOVER_IMAGE + bool + default n + depends on BOARD_TYAN_S2892 + +config HW_MEM_HOLE_SIZEK + hex + default 0x100000 + depends on BOARD_TYAN_S2892 + +config MEM_TRAIN_SEQ + bool + default n + depends on BOARD_TYAN_S2892 + +config HAVE_FAILOVER_BOOT + bool + default n + depends on BOARD_TYAN_S2892 + +config USE_FAILOVER_IMAGE + bool + default n + depends on BOARD_TYAN_S2892 + +config MAX_CPUS + int + default 4 + depends on BOARD_TYAN_S2892 + +config MAX_PHYSICAL_CPUS + int + default 2 + depends on BOARD_TYAN_S2892 + +config MEM_TRAIN_SEQ + bool + default n + depends on BOARD_TYAN_S2892 + +config AP_CODE_IN_CAR + bool + default n + depends on BOARD_TYAN_S2892 + +config HW_MEM_HOLE_SIZE_AUTO_INC + bool + default n + depends on BOARD_TYAN_S2892 + +config HT_CHAIN_UNITID_BASE + hex + default 0 + depends on BOARD_TYAN_S2892 + +config HT_CHAIN_END_UNITID_BASE + hex + default 0x20 + depends on BOARD_TYAN_S2892 + +config USE_INIT + bool + default n + depends on BOARD_TYAN_S2892 + +config SERIAL_CPU_INIT + bool + default y + depends on BOARD_TYAN_S2892 + +config AP_CODE_IN_CAR + bool + default y + depends on BOARD_TYAN_S2892 + +config WAIT_BEFORE_CPUS_INIT + bool + default n + depends on BOARD_TYAN_S2892 + +config SB_HT_CHAIN_ON_BUS0 + int + default 2 + depends on BOARD_TYAN_S2892 + +config SB_HT_CHAIN_UNITID_OFFSET_ONLY + bool + default n + depends on BOARD_TYAN_S2892 + +config HAVE_ACPI_TABLES + bool "Generate ACPI tables" + default y + depends on BOARD_TYAN_S2892 + Property changes on: trunk/coreboot-v2/src/mainboard/tyan/s2892/Kconfig ___________________________________________________________________ Added: svn:mergeinfo + Added: trunk/coreboot-v2/src/mainboard/tyan/s2892/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2892/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/mainboard/tyan/s2892/Makefile.inc 2009-09-22 18:53:50 UTC (rev 4656) @@ -0,0 +1,3 @@ +include $(src)/mainboard/tyan/Makefile.s289x.inc + +driver-y += ../../../drivers/i2c/adm1027/adm1027.o Modified: trunk/coreboot-v2/src/mainboard/tyan/s2895/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2895/Config.lb 2009-09-22 18:49:08 UTC (rev 4655) +++ trunk/coreboot-v2/src/mainboard/tyan/s2895/Config.lb 2009-09-22 18:53:50 UTC (rev 4656) @@ -29,25 +29,10 @@ end if CONFIG_USE_INIT -if CONFIG_USE_FAILOVER_IMAGE makerule ./auto.o - depends "$(CONFIG_MAINBOARD)/failover.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/failover.c -o $@" - end -else - makerule ./auto.o depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" end -end -else #CONFIG_USE_INIT -if CONFIG_USE_FAILOVER_IMAGE - makerule ./auto.inc - depends "$(CONFIG_MAINBOARD)/failover.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/failover.c -o $@" - action "perl -e 's/\.rodata/.rom.data/g' -pi $@" - action "perl -e 's/\.text/.section .rom.text/g' -pi $@" - end else makerule ./auto.inc depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" @@ -56,32 +41,51 @@ action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end end -end #CONFIG_USE_INIT ## ## Build our 16 bit and 32 bit coreboot entry code ## -if CONFIG_USE_FAILOVER_IMAGE - mainboardinit cpu/x86/16bit/entry16.inc - ldscript /cpu/x86/16bit/entry16.lds +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE + mainboardinit cpu/x86/16bit/entry16.inc + ldscript /cpu/x86/16bit/entry16.lds + end +else + if CONFIG_USE_FALLBACK_IMAGE + mainboardinit cpu/x86/16bit/entry16.inc + ldscript /cpu/x86/16bit/entry16.lds + end end mainboardinit cpu/x86/32bit/entry32.inc if CONFIG_USE_INIT ldscript /cpu/x86/32bit/entry32.lds + end + + if CONFIG_USE_INIT ldscript /cpu/amd/car/cache_as_ram.lds end ## ## Build our reset vector (This is where coreboot is entered) ## -if CONFIG_USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds + else + mainboardinit cpu/x86/32bit/reset32.inc + ldscript /cpu/x86/32bit/reset32.lds + end else + if CONFIG_USE_FALLBACK_IMAGE + mainboardinit cpu/x86/16bit/reset16.inc + ldscript /cpu/x86/16bit/reset16.lds + else mainboardinit cpu/x86/32bit/reset32.inc ldscript /cpu/x86/32bit/reset32.lds + end end ## @@ -93,9 +97,16 @@ ## ## ROMSTRAP table for CK804 ## -if CONFIG_USE_FAILOVER_IMAGE - mainboardinit southbridge/nvidia/ck804/romstrap.inc - ldscript /southbridge/nvidia/ck804/romstrap.lds +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE + mainboardinit southbridge/nvidia/ck804/romstrap.inc + ldscript /southbridge/nvidia/ck804/romstrap.lds + end +else + if CONFIG_USE_FALLBACK_IMAGE + mainboardinit southbridge/nvidia/ck804/romstrap.inc + ldscript /southbridge/nvidia/ck804/romstrap.lds + end end ## @@ -108,8 +119,14 @@ ### Things are delicate and we test to see if we should ### failover to another image. ### -if CONFIG_USE_FAILOVER_IMAGE - ldscript /arch/i386/lib/failover_failover.lds +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE + ldscript /arch/i386/lib/failover_failover.lds + end +else + if CONFIG_USE_FALLBACK_IMAGE + ldscript /arch/i386/lib/failover.lds + end end ## Copied: trunk/coreboot-v2/src/mainboard/tyan/s2895/Kconfig (from rev 4611, trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Kconfig) =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2895/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/tyan/s2895/Kconfig 2009-09-22 18:53:50 UTC (rev 4656) @@ -0,0 +1,142 @@ +config BOARD_TYAN_S2895 + bool "Tyan Thunder K8WE S2895" + select ARCH_X86 + select CPU_AMD_K8 + select CPU_AMD_SOCKET_940 + select NORTHBRIDGE_AMD_AMDK8 + select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX + select SOUTHBRIDGE_NVIDIA_CK804 + select SOUTHBRIDGE_AMD_AMD8131 + select SUPERIO_SMSC_LPC47B397 + select PIRQ_TABLE + +config MAINBOARD_DIR + string + default tyan/s2895 + depends on BOARD_TYAN_S2895 + +config APIC_ID_OFFSET + hex + default 8 + depends on BOARD_TYAN_S2895 + +config SB_HT_CHAIN_ON_BUS0 + int + default 2 + depends on BOARD_TYAN_S2895 + +config LB_CKS_RANGE_END + int + default 122 + depends on BOARD_TYAN_S2895 + +config LB_CKS_LOC + int + default 123 + depends on BOARD_TYAN_S2895 + +config MAINBOARD_PART_NUMBER + string + default "s2895" + depends on BOARD_TYAN_S2895 + +config CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID + hex + default 0x2895 + depends on BOARD_TYAN_S2895 + +config USE_FAILOVER_IMAGE + bool + default n + depends on BOARD_TYAN_S2895 + +config HW_MEM_HOLE_SIZEK + hex + default 0x100000 + depends on BOARD_TYAN_S2895 + +config MEM_TRAIN_SEQ + bool + default n + depends on BOARD_TYAN_S2895 + +config HAVE_FAILOVER_BOOT + bool + default n + depends on BOARD_TYAN_S2895 + +config USE_FAILOVER_IMAGE + bool + default n + depends on BOARD_TYAN_S2895 + +config MAX_CPUS + int + default 4 + depends on BOARD_TYAN_S2895 + +config MAX_PHYSICAL_CPUS + int + default 2 + depends on BOARD_TYAN_S2895 + +config MEM_TRAIN_SEQ + bool + default n + depends on BOARD_TYAN_S2895 + +config AP_CODE_IN_CAR + bool + default n + depends on BOARD_TYAN_S2895 + +config HW_MEM_HOLE_SIZE_AUTO_INC + bool + default n + depends on BOARD_TYAN_S2895 + +config HT_CHAIN_UNITID_BASE + hex + default 0 + depends on BOARD_TYAN_S2895 + +config HT_CHAIN_END_UNITID_BASE + hex + default 0x20 + depends on BOARD_TYAN_S2895 + +config USE_INIT + bool + default n + depends on BOARD_TYAN_S2895 + +config SERIAL_CPU_INIT + bool + default y + depends on BOARD_TYAN_S2895 + +config AP_CODE_IN_CAR + bool + default y + depends on BOARD_TYAN_S2895 + +config WAIT_BEFORE_CPUS_INIT + bool + default n + depends on BOARD_TYAN_S2895 + +config SB_HT_CHAIN_ON_BUS0 + int + default 2 + depends on BOARD_TYAN_S2895 + +config SB_HT_CHAIN_UNITID_OFFSET_ONLY + bool + default n + depends on BOARD_TYAN_S2895 + +config HAVE_ACPI_TABLES + bool "Generate ACPI tables" + default y + depends on BOARD_TYAN_S2895 + Property changes on: trunk/coreboot-v2/src/mainboard/tyan/s2895/Kconfig ___________________________________________________________________ Added: svn:mergeinfo + Added: trunk/coreboot-v2/src/mainboard/tyan/s2895/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2895/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/mainboard/tyan/s2895/Makefile.inc 2009-09-22 18:53:50 UTC (rev 4656) @@ -0,0 +1 @@ +include $(src)/mainboard/tyan/Makefile.s289x.inc Modified: trunk/coreboot-v2/src/mainboard/tyan/s2895/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2895/cache_as_ram_auto.c 2009-09-22 18:49:08 UTC (rev 4655) +++ trunk/coreboot-v2/src/mainboard/tyan/s2895/cache_as_ram_auto.c 2009-09-22 18:53:50 UTC (rev 4656) @@ -1,3 +1,4 @@ +#define ASSEMBLY 1 #define __ROMCC__ #define K8_ALLOCATE_IO_RANGE 1 @@ -20,12 +21,11 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" -#define post_code(x) outb(x, 0x80) +#if CONFIG_USE_FAILOVER_IMAGE==0 #include "pc80/serial.c" #include "arch/i386/lib/console.c" #include "ram/ramtest.c" - #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/incoherent_ht.c" @@ -34,6 +34,8 @@ #include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" +#endif + #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" #include "superio/smsc/lpc47b397/lpc47b397_early_serial.c" @@ -42,6 +44,8 @@ #define SUPERIO_GPIO_IO_BASE 0x400 +#if CONFIG_USE_FAILOVER_IMAGE==0 + #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/debug.c" @@ -114,8 +118,117 @@ #include "cpu/amd/model_fxx/init_cpus.c" +#endif + +#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1)) + +#include "southbridge/nvidia/ck804/ck804_enable_rom.c" +#include "northbridge/amd/amdk8/early_ht.c" + +static void sio_setup(void) +{ + + unsigned value; + uint32_t dword; + uint8_t byte; + + pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1, 0), 0xac, 0x047f0400); + + byte = pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b); + byte |= 0x20; + pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte); + + dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0); + dword |= (1<<29)|(1<<0); + pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword); + + dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1, 0), 0xa4); + dword |= (1<<16); + pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa4, dword); + + lpc47b397_enable_serial(SUPERIO_GPIO_DEV, SUPERIO_GPIO_IO_BASE); + value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x77); + value &= 0xbf; + lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x77, value); + +} + +void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) +{ + unsigned last_boot_normal_x = last_boot_normal(); + + /* Is this a cpu only reset? or Is this a secondary cpu? */ + if ((cpu_init_detectedx) || (!boot_cpu())) { + if (last_boot_normal_x) { + goto normal_image; + } else { + goto fallback_image; + } + } + + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + + enumerate_ht_chain(); + + sio_setup(); + + /* Setup the ck804 */ + ck804_enable_rom(); + + /* Is this a deliberate reset by the bios */ +// post_code(0x22); + if (bios_reset_detected() && last_boot_normal_x) { + goto normal_image; + } + /* This is the primary cpu how should I boot? */ + else if (do_normal_boot()) { + goto normal_image; + } + else { + goto fallback_image; + } + normal_image: +// post_code(0x23); + __asm__ volatile ("jmp __normal_image" + : /* outputs */ + : "a" (bist), "b"(cpu_init_detectedx) /* inputs */ + ); + + fallback_image: +// post_code(0x25); +#if CONFIG_HAVE_FAILOVER_BOOT==1 + __asm__ volatile ("jmp __fallback_image" + : /* outputs */ + : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ + ) +#endif + ; +} +#endif + +void real_main(unsigned long bist, unsigned long cpu_init_detectedx); + void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { +#if CONFIG_HAVE_FAILOVER_BOOT==1 + #if CONFIG_USE_FAILOVER_IMAGE==1 + failover_process(bist, cpu_init_detectedx); + #else + real_main(bist, cpu_init_detectedx); + #endif +#else + #if CONFIG_USE_FALLBACK_IMAGE == 1 + failover_process(bist, cpu_init_detectedx); + #endif + real_main(bist, cpu_init_detectedx); +#endif +} + +#if CONFIG_USE_FAILOVER_IMAGE==0 + +void real_main(unsigned long bist, unsigned long cpu_init_detectedx) +{ static const uint16_t spd_addr [] = { (0xa<<3)|0, (0xa<<3)|2, 0, 0, (0xa<<3)|1, (0xa<<3)|3, 0, 0, @@ -135,7 +248,7 @@ bsp_apicid = init_cpus(cpu_init_detectedx); } - post_code(0x32); +// post_code(0x32); lpc47b397_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); @@ -197,3 +310,4 @@ post_cache_as_ram(); } +#endif Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/Kconfig =================================================================== --- trunk/coreboot-v2/src/southbridge/nvidia/ck804/Kconfig 2009-09-22 18:49:08 UTC (rev 4655) +++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/Kconfig 2009-09-22 18:53:50 UTC (rev 4656) @@ -1,3 +1,14 @@ config SOUTHBRIDGE_NVIDIA_CK804 bool default n + +config HAVE_HARD_RESET + bool + default y + depends on SOUTHBRIDGE_NVIDIA_CK804 + +config IOAPIC + bool + default y + depends on SOUTHBRIDGE_NVIDIA_CK804 + Modified: trunk/coreboot-v2/targets/tyan/s2895/Config-abuild.lb =================================================================== --- trunk/coreboot-v2/targets/tyan/s2895/Config-abuild.lb 2009-09-22 18:49:08 UTC (rev 4655) +++ trunk/coreboot-v2/targets/tyan/s2895/Config-abuild.lb 2009-09-22 18:53:50 UTC (rev 4656) @@ -24,11 +24,4 @@ payload __PAYLOAD__ end -romimage "failover" - option CONFIG_USE_FAILOVER_IMAGE=1 - option CONFIG_USE_FALLBACK_IMAGE=0 - option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE - option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE -end - -buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" Modified: trunk/coreboot-v2/targets/tyan/s2895/Config.lb =================================================================== --- trunk/coreboot-v2/targets/tyan/s2895/Config.lb 2009-09-22 18:49:08 UTC (rev 4655) +++ trunk/coreboot-v2/targets/tyan/s2895/Config.lb 2009-09-22 18:53:50 UTC (rev 4656) @@ -7,80 +7,21 @@ # Tyan s2895 romimage "normal" -# 48K for SCSI FW -# option CONFIG_ROM_SIZE = 475136 -# 48K for SCSI FW and 48K for ATI ROM -# option CONFIG_ROM_SIZE = 425984 -# 64K for Etherboot -# option CONFIG_ROM_SIZE = 458752 -# 64K for NIC option 48K for Raid option rom -# option CONFIG_ROM_SIZE = 409600 option CONFIG_USE_FAILOVER_IMAGE=0 option CONFIG_USE_FALLBACK_IMAGE=0 -# option CONFIG_ROM_IMAGE_SIZE=0x11800 -# option CONFIG_ROM_IMAGE_SIZE=0x13800 -# option CONFIG_ROM_IMAGE_SIZE=0x15000 option CONFIG_ROM_IMAGE_SIZE=0x20000 -# option CONFIG_ROM_IMAGE_SIZE=0x17800 option CONFIG_XIP_ROM_SIZE=0x20000 option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal" -# payload ../../../payloads/tg3--ide_disk.zelf -# payload ../../../payloads/filo.elf -# payload ../../../payloads/filo_mem.elf -# payload ../../../payloads/filo.zelf -# payload ../../../payloads/tg3.zelf -# payload ../../../payloads/tg3--filo_hda2_vga.zelf -# payload ../../../../payloads/forcedeth--filo_hda2_vga.zelf -# payload ../../../payloads/forcedeth_vga.zelf -# payload ../../../payloads/forcedeth--filo_hda2_vga_5_4.zelf -# payload ../../../../../../elf/ram0_2.5_2.6.11.tiny.elf -# payload ../../../../../../elf/ram0_2.5_2.6.12.tiny.elf -# payload ../../../payloads/tg3--filo_hda2_vga_5_4.zelf -# payload ../../../payloads/tg3_vga.zelf -# payload ../../../payloads/tg3--filo_hda2_vgax.zelf -# payload ../../../payloads/tg3--filo_hda2_com2.zelf -# payload ../../../payloads/e1000--filo.zelf -# payload ../../../payloads/tg3--e1000--filo.zelf -# payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf payload ../payload.elf end romimage "fallback" option CONFIG_USE_FAILOVER_IMAGE=0 option CONFIG_USE_FALLBACK_IMAGE=1 -# option CONFIG_ROM_IMAGE_SIZE=0x11800 -# option CONFIG_ROM_IMAGE_SIZE=0x13800 -# option CONFIG_ROM_IMAGE_SIZE=0x15000 option CONFIG_ROM_IMAGE_SIZE=0x20000 -# option CONFIG_ROM_IMAGE_SIZE=0x17800 option CONFIG_XIP_ROM_SIZE=0x20000 option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" -# payload ../../../payloads/tg3--ide_disk.zelf -# payload ../../../payloads/filo.elf -# payload ../../../payloads/filo_mem.elf -# payload ../../../payloads/filo.zelf -# payload ../../../payloads/tg3.zelf -# payload ../../../payloads/tg3--filo_hda2_vga.zelf -# payload ../../../../payloads/forcedeth--filo_hda2_vga.zelf -# payload ../../../payloads/forcedeth_vga.zelf -# payload ../../../payloads/tg3--filo_hda2_vga_5_4.zelf -# payload ../../../payloads/tg3_vga.zelf -# payload ../../../payloads/tg3--filo_hda2_vgax.zelf -# payload ../../../payloads/tg3--filo_hda2_com2.zelf -# payload ../../../payloads/e1000--filo.zelf -# payload ../../../payloads/tg3--e1000--filo.zelf -# payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf payload ../payload.elf end -romimage "failover" - option CONFIG_USE_FAILOVER_IMAGE=1 - option CONFIG_USE_FALLBACK_IMAGE=0 - option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE - option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE - option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover" -end - - -buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover" -#buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" -- coreboot mailing list: [email protected] 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