On Wed, Sep 23, 2009 at 06:03:38AM +0200, Daniel Mack wrote: > On Tue, Sep 22, 2009 at 01:56:53PM +0200, Peter Stuge wrote: > > > > Check out the 5536 data book on "Atomic Bit Programming" and/or look > > at the Linux LED driver for reference. To program the GPIOs you have > > to follow the algorithm outlined in 6.16.1. > > Hmm. I followed that guideline, and did the same thing than the Linux > driver, but it still doesn't work. I only found one location from where > I could successfully write to the GPIO registers, and that is > hardware_stage1() in mainboard/pcengines/alix2c3/stage.c. > > When moving the same code to southbridge_init() in > southbridge/amd/cs5536/cs5536.c, the register accesses fail. > > Also, when booting Linux, the LED driver does not work with coreboot > for me. The register space mapping seems to be given up at some point > on the way, but I can't figure out where and why yet. As I don't know > coreboot's internals, I'd appreciate any pointer.
I traced a little further and implemented a cs5536_set_resources() which simply wraps the call to pci_set_resources(). GPIO registers are accessed ok before pci_set_resources() but fail after. This is the output of print_resource_tree() of the device used: (CB) PCI: 00:0f.0 links 0 child on link 0 NULL (CB) PCI: 00:0f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags e0000100 index 0 (CB) PCI: 00:0f.0 resource base 20b0 size 8 align 3 gran 3 limit ffff flags 40000100 index 10 (CB) PCI: 00:0f.0 resource base 1800 size 100 align 8 gran 8 limit ffff flags 40000100 index 14 (CB) PCI: 00:0f.0 resource base 2000 size 40 align 6 gran 6 limit ffff flags 40000100 index 18 (CB) PCI: 00:0f.0 resource base 2080 size 20 align 5 gran 5 limit ffff flags 40000100 index 1c (CB) PCI: 00:0f.0 resource base 1c00 size 80 align 7 gran 7 limit ffff flags 40000100 index 20 (CB) PCI: 00:0f.0 resource base 2040 size 40 align 6 gran 6 limit ffff flags 40000100 index 24 Any ideas? Daniel -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
