Index: gpio.c
===================================================================
--- gpio.c	(revision 4668)
+++ gpio.c	(working copy)
@@ -131,6 +131,9 @@
 		gpio_registers = ich0_gpio_registers;
 		size = ARRAY_SIZE(ich0_gpio_registers);
 		break;
+	case PCI_DEVICE_ID_INTEL_82371:
+		printf("This southbridge has GPIO in Power Management Unit.\n");
+		return 1;
 	case 0x1234: // Dummy for non-existent functionality
 		printf("This southbridge does not have GPIOBASE.\n");
 		return 1;
Index: inteltool.h
===================================================================
--- inteltool.h	(revision 4668)
+++ inteltool.h	(working copy)
@@ -54,6 +54,16 @@
 #define PCI_DEVICE_ID_INTEL_82975X	0x277c
 #define PCI_DEVICE_ID_INTEL_X58	0x3405
 
+#define PCI_DEVICE_ID_INTEL_82443LX	0x7180
+/* according to datasheet DID is different whatever if AGP_DIS bit in PMCR register is set or cleared
+*/
+#define PCI_DEVICE_ID_INTEL_82443BX	0x7190
+#define PCI_DEVICE_ID_INTEL_82443BX_2	0x7192
+
+/* AB MB and EB versions use SAME DID value
+*/
+#define PCI_DEVICE_ID_INTEL_82371	0x7110
+
 #define ARRAY_SIZE(a) ((int)(sizeof(a) / sizeof((a)[0])))
 
 #ifndef __DARWIN__
Index: powermgt.c
===================================================================
--- powermgt.c	(revision 4668)
+++ powermgt.c	(working copy)
@@ -203,6 +203,48 @@
 	{ 0x7c, 4, "RESERVED" },
 };
 
+static const io_register_t i371_pm_registers[] = {
+	{ 0x00, 2, "PMSTS" },
+	{ 0x02, 2, "PMEN" },
+	{ 0x04, 2, "PMCNT" },
+	{ 0x06, 2, "RESERVED" },
+	{ 0x08, 1, "PMTMR" },
+	{ 0x09, 1, "RESERVED" },
+	{ 0x0B, 2, "RESERVED" },
+	{ 0x0C, 2, "GPSTS" },
+	{ 0x0E, 2, "GPEN" },
+	{ 0x10, 4, "PCNTRL" },
+#if DANGEROUS_REGISTERS
+	/* This register returns 0 on read, but reading it may cause
+	 * the system to enter C2 state, which might hang the system.
+	 */
+	{ 0x14, 1, "PLVL2" },
+	{ 0x15, 1, "PLVL3" },
+	{ 0x16, 2, "RESERVED" },
+#endif
+	{ 0x18, 2, "GLBSTS" },
+	{ 0x1A, 2, "RESERVED" },
+	{ 0x1c, 4, "DEVSTS" },
+	{ 0x20, 2, "GLBEN" },
+	{ 0x22, 2, "RESERVED" },
+	{ 0x24, 4, "RESERVED" },
+	{ 0x28, 4, "GLBCTL" },
+	{ 0x2C, 4, "DEVCTL" },
+	/* datasheet says BYTE reads so i assume that i should do them 
+	 * that way to get byte reads. And data read differ if code
+	 * do reads in larger than byte chunks.
+	 */
+	{ 0x30, 1, "GPIREG 0" },
+	{ 0x31, 1, "GPIREG 1" },
+	{ 0x32, 1, "GPIREG 2" },
+	{ 0x33, 1, "GPIREG 3" },
+	{ 0x34, 1, "GPOREG 0" },
+	{ 0x35, 1, "GPOREG 1" },
+	{ 0x36, 1, "GPOREG 2" },
+	{ 0x37, 1, "GPOREG 3" },
+};
+
+
 int print_pmbase(struct pci_dev *sb)
 {
 	int i, size;
@@ -230,6 +272,11 @@
 		pm_registers = ich0_pm_registers;
 		size = ARRAY_SIZE(ich0_pm_registers);
 		break;
+	case PCI_DEVICE_ID_INTEL_82371:
+		pmbase = pci_read_word(sb, 0x40) & 0xfffc;
+		pm_registers = i371_pm_registers;
+		size = ARRAY_SIZE(ich0_pm_registers);
+		break;
 	case 0x1234: // Dummy for non-existent functionality
 		printf("This southbridge does not have PMBASE.\n");
 		return 1;
Index: memory.c
===================================================================
--- memory.c	(revision 4668)
+++ memory.c	(working copy)
@@ -45,6 +45,9 @@
  		break;
 	case PCI_DEVICE_ID_INTEL_82810:
 	case PCI_DEVICE_ID_INTEL_82810DC:
+	/* datasheets don't mention anything like MCHBAR */
+	case PCI_DEVICE_ID_INTEL_82443BX:
+	case PCI_DEVICE_ID_INTEL_82443LX:
 		printf("This northbrigde does not have MCHBAR.\n");
 		return 1;
 	default:
Index: inteltool.c
===================================================================
--- inteltool.c	(revision 4668)
+++ inteltool.c	(working copy)
@@ -47,7 +47,12 @@
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH4, "ICH4" },
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH2, "ICH2" },
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH0, "ICH0" },
-	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH, "ICH" }
+	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH, "ICH" },
+
+	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX, "i443LX" },
+	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX, "i443BX" },
+	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, "i443BX -AGP" }, /* AGP DISABLED */
+	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371, "i371" }
 };
 
 #ifndef __DARWIN__
@@ -121,6 +126,7 @@
 	int dump_gpios = 0, dump_mchbar = 0, dump_rcba = 0;
 	int dump_pmbase = 0, dump_epbar = 0, dump_dmibar = 0;
 	int dump_pciexbar = 0, dump_coremsrs = 0;
+	int workaround = 0;
 
 	static struct option long_options[] = {
 		{"version", 0, 0, 'v'},
@@ -134,10 +140,11 @@
 		{"pciexpress", 0, 0, 'P'},
 		{"msrs", 0, 0, 'M'},
 		{"all", 0, 0, 'a'},
+		{"workaround", 0, 0, 'w'},
 		{0, 0, 0, 0}
 	};
 
-	while ((opt = getopt_long(argc, argv, "vh?grpmedPMa",
+	while ((opt = getopt_long(argc, argv, "vh?grpmedPMaw",
                                   long_options, &option_index)) != EOF) {
 		switch (opt) {
 		case 'v':
@@ -178,6 +185,9 @@
 			dump_pciexbar = 1;
 			dump_coremsrs = 1;
 			break;
+		case 'w':
+			workaround = 1;
+			break;
 		case 'h':
 		case '?':
 		default:
@@ -205,7 +215,15 @@
 
 	/* Find the required devices */
 
-	sb = pci_get_dev(pacc, 0, 0, 0x1f, 0);
+	if (workaround == 1) 
+		sb = pci_get_dev(pacc, 0, 0, 0x07, 0);
+	else
+		sb = pci_get_dev(pacc, 0, 0, 0x1f, 0);
+
+	/* Older Intel systems have their southbridge at 0:7.0 */
+	if (!sb) 
+		sb = pci_get_dev(pacc, 0, 0, 0x07, 0);
+
 	if (!sb) {
 		printf("No southbridge found.\n");
 		exit(1);