On Thu, Oct 01, 2009 at 11:15:32AM -0700, ron minnich wrote: > But I need to inlude the sse regiisters. > > Here is a possibility > > crt0-$(CONFIG_CPU_INTEL_P4) += ../../../../src/cpu/x86/sse/enable_sse.inc > > that ok? I can put that in.
Here's what I did for GX1 support (patch not yet finished and not yet submitted): +ifeq ($(CONFIG_CPU_AMD_GX1),y) +crt0-y += ../../../../src/cpu/amd/model_gx1/cpu_setup.inc +crt0-y += ../../../../src/cpu/amd/model_gx1/gx_setup.inc +crt0-y += auto.inc +else crt0-y += ../../../../src/cpu/x86/mmx/enable_mmx.inc crt0-y += auto.inc crt0-y += ../../../../src/cpu/x86/mmx/disable_mmx.inc +endif Something similar can be done for SSE, probably with a kconfig variable CONFIG_HAVE_SSE which is set (or not) per board or more likely per chipset. Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
