Author: oxygene Date: 2009-10-03 18:27:48 +0200 (Sat, 03 Oct 2009) New Revision: 4713
Modified: trunk/coreboot-v2/src/mainboard/artecgroup/dbe61/realmode/vgabios.c trunk/coreboot-v2/src/mainboard/via/epia-m/vgabios.c trunk/coreboot-v2/src/northbridge/via/cn400/vgabios.c trunk/coreboot-v2/src/northbridge/via/cn700/vgabios.c trunk/coreboot-v2/src/northbridge/via/cx700/vgabios.c trunk/coreboot-v2/src/northbridge/via/vx800/vgabios.c Log: Tell vgabios code in a couple of boards/chipsets about CBFS Signed-off-by: Patrick Georgi <[email protected]> Acked-by: Stefan Reinauer <[email protected]> Modified: trunk/coreboot-v2/src/mainboard/artecgroup/dbe61/realmode/vgabios.c =================================================================== --- trunk/coreboot-v2/src/mainboard/artecgroup/dbe61/realmode/vgabios.c 2009-10-03 16:24:58 UTC (rev 4712) +++ trunk/coreboot-v2/src/mainboard/artecgroup/dbe61/realmode/vgabios.c 2009-10-03 16:27:48 UTC (rev 4713) @@ -7,6 +7,7 @@ #include <arch/io.h> #include <string.h> #include "chip.h" +#include <cbfs.h> /* vgabios.c. Derived from: */ @@ -266,7 +267,7 @@ { unsigned long busdevfn; - unsigned int rom = dev->rom_address; + unsigned int rom = cbfs_load_optionrom(dev->vendor, dev->device, 0); unsigned char *buf; unsigned int size = 64*1024; int i; Modified: trunk/coreboot-v2/src/mainboard/via/epia-m/vgabios.c =================================================================== --- trunk/coreboot-v2/src/mainboard/via/epia-m/vgabios.c 2009-10-03 16:24:58 UTC (rev 4712) +++ trunk/coreboot-v2/src/mainboard/via/epia-m/vgabios.c 2009-10-03 16:27:48 UTC (rev 4713) @@ -7,6 +7,7 @@ //#include <printk.h> #include <string.h> #include "vgachip.h" +#include <cbfs.h> /* vgabios.c. Derived from: */ @@ -356,7 +357,7 @@ /* declare rom address here - keep any config data out of the way * of core LXB stuff */ - rom = 0xfffc0000; + rom = (unsigned int)cbfs_load_optionrom(dev->vendor, dev->device, 0); pci_write_config32(dev, PCI_ROM_ADDRESS, rom|1); printk_debug("rom base, size: %x\n", rom); Modified: trunk/coreboot-v2/src/northbridge/via/cn400/vgabios.c =================================================================== --- trunk/coreboot-v2/src/northbridge/via/cn400/vgabios.c 2009-10-03 16:24:58 UTC (rev 4712) +++ trunk/coreboot-v2/src/northbridge/via/cn400/vgabios.c 2009-10-03 16:27:48 UTC (rev 4713) @@ -7,6 +7,7 @@ //#include <printk.h> #include <string.h> #include "vgachip.h" +#include <cbfs.h> /* vgabios.c. Derived from: */ @@ -356,7 +357,7 @@ /* declare rom address here - keep any config data out of the way * of core LXB stuff */ - rom = 0xfff80000; + rom = cbfs_load_optionrom(dev->vendor, dev->device, 0); pci_write_config32(dev, PCI_ROM_ADDRESS, rom|1); printk_debug("VGA BIOS ROM base address: %x\n", rom); Modified: trunk/coreboot-v2/src/northbridge/via/cn700/vgabios.c =================================================================== --- trunk/coreboot-v2/src/northbridge/via/cn700/vgabios.c 2009-10-03 16:24:58 UTC (rev 4712) +++ trunk/coreboot-v2/src/northbridge/via/cn700/vgabios.c 2009-10-03 16:27:48 UTC (rev 4713) @@ -7,6 +7,7 @@ //#include <printk.h> #include <string.h> #include "vgachip.h" +#include <cbfs.h> /* vgabios.c. Derived from: */ @@ -356,7 +357,7 @@ /* declare rom address here - keep any config data out of the way * of core LXB stuff */ - rom = 0xfff80000; + rom = cbfs_load_optionrom(dev->vendor, dev->device, 0); pci_write_config32(dev, PCI_ROM_ADDRESS, rom|1); printk_debug("rom base, size: %x\n", rom); Modified: trunk/coreboot-v2/src/northbridge/via/cx700/vgabios.c =================================================================== --- trunk/coreboot-v2/src/northbridge/via/cx700/vgabios.c 2009-10-03 16:24:58 UTC (rev 4712) +++ trunk/coreboot-v2/src/northbridge/via/cx700/vgabios.c 2009-10-03 16:27:48 UTC (rev 4713) @@ -28,6 +28,7 @@ #undef __KERNEL__ #include <arch/io.h> #include <string.h> +#include <cbfs.h> void write_protect_vgabios(void); @@ -323,7 +324,7 @@ * of core LXB stuff */ #warning ROM address hardcoded to 512K - rom = 0xfff80000; + rom = (unsigned int)cbfs_load_optionrom(dev->vendor, dev->device, 0); pci_write_config32(dev, PCI_ROM_ADDRESS, rom | 1); printk_debug("rom base, size: %x\n", rom); Modified: trunk/coreboot-v2/src/northbridge/via/vx800/vgabios.c =================================================================== --- trunk/coreboot-v2/src/northbridge/via/vx800/vgabios.c 2009-10-03 16:24:58 UTC (rev 4712) +++ trunk/coreboot-v2/src/northbridge/via/vx800/vgabios.c 2009-10-03 16:27:48 UTC (rev 4713) @@ -6,6 +6,7 @@ #include <arch/io.h> #include <string.h> #include "vgachip.h" +#include <cbfs.h> /* vgabios.c. Derived from: */ @@ -319,7 +320,7 @@ /* declare rom address here - keep any config data out of the way * of core LXB stuff */ - rom = 0xffffffff - CONFIG_ROM_SIZE + 1; + rom = cbfs_load_optionrom(dev->vendor, dev->device, 0); pci_write_config32(dev, PCI_ROM_ADDRESS, rom | 1); printk_debug("rom base: %x\n", rom); buf = (unsigned char *)rom; -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
