Author: myles Date: 2009-10-16 18:32:57 +0200 (Fri, 16 Oct 2009) New Revision: 4788
Modified: trunk/coreboot-v2/src/Kconfig trunk/coreboot-v2/src/config/Options.lb trunk/coreboot-v2/src/config/coreboot_ram.ld trunk/coreboot-v2/src/console/usbdebug_direct_console.c trunk/coreboot-v2/src/cpu/amd/car/cache_as_ram.inc trunk/coreboot-v2/src/cpu/amd/car/clear_init_ram.c trunk/coreboot-v2/src/cpu/amd/car/post_cache_as_ram.c trunk/coreboot-v2/src/cpu/amd/model_fxx/model_fxx_init.c trunk/coreboot-v2/src/cpu/amd/mtrr/amd_earlymtrr.c trunk/coreboot-v2/src/cpu/x86/lapic/lapic_cpu_init.c trunk/coreboot-v2/src/cpu/x86/mtrr/earlymtrr.c trunk/coreboot-v2/src/cpu/x86/pae/pgtbl.c trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Options.lb trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/apc_auto.c trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/apc_auto.c trunk/coreboot-v2/src/mainboard/asus/a8n_e/Options.lb trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/Options.lb trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/Options.lb trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/mainboard.c trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/Options.lb trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/apc_auto.c trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Options.lb trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/apc_auto.c trunk/coreboot-v2/src/mainboard/hp/dl145_g3/Options.lb trunk/coreboot-v2/src/mainboard/intel/truxton/Options.lb trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/Options.lb trunk/coreboot-v2/src/mainboard/msi/ms7135/Options.lb trunk/coreboot-v2/src/mainboard/msi/ms7260/Options.lb trunk/coreboot-v2/src/mainboard/msi/ms7260/apc_auto.c trunk/coreboot-v2/src/mainboard/msi/ms9185/Options.lb trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/Options.lb trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/apc_auto.c trunk/coreboot-v2/src/mainboard/supermicro/h8dme/Options.lb trunk/coreboot-v2/src/mainboard/supermicro/h8dme/apc_auto.c trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/Options.lb trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/apc_auto.c trunk/coreboot-v2/src/mainboard/supermicro/h8dmr_fam10/Options.lb trunk/coreboot-v2/src/mainboard/supermicro/h8dmr_fam10/apc_auto.c trunk/coreboot-v2/src/mainboard/tyan/s2885/Options.lb trunk/coreboot-v2/src/mainboard/tyan/s2891/Options.lb trunk/coreboot-v2/src/mainboard/tyan/s2892/Options.lb trunk/coreboot-v2/src/mainboard/tyan/s2895/Options.lb trunk/coreboot-v2/src/mainboard/tyan/s2912/Options.lb trunk/coreboot-v2/src/mainboard/tyan/s2912/apc_auto.c trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/Options.lb trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/apc_auto.c trunk/coreboot-v2/src/mainboard/via/epia-n/Options.lb trunk/coreboot-v2/src/northbridge/amd/amdfam10/amdfam10_acpi.c trunk/coreboot-v2/src/northbridge/amd/amdfam10/northbridge.c trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit.c trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit_f.c trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit_f_dqs.c trunk/coreboot-v2/src/pc80/usbdebug_direct_serial.c Log: Change CONFIG_LB_MEM_TOPK to CONFIG_RAMTOP to match CONFIG_RAMBASE. Signed-off-by: Myles Watson <[email protected]> Acked-by: Peter Stuge <[email protected]> Modified: trunk/coreboot-v2/src/Kconfig =================================================================== --- trunk/coreboot-v2/src/Kconfig 2009-10-16 14:34:50 UTC (rev 4787) +++ trunk/coreboot-v2/src/Kconfig 2009-10-16 16:32:57 UTC (rev 4788) @@ -134,9 +134,9 @@ bool default n -config LB_MEM_TOPK +config RAMTOP hex - default 0x800 + default 0x200000 config COMPRESSED_PAYLOAD_LZMA bool Modified: trunk/coreboot-v2/src/config/Options.lb =================================================================== --- trunk/coreboot-v2/src/config/Options.lb 2009-10-16 14:34:50 UTC (rev 4787) +++ trunk/coreboot-v2/src/config/Options.lb 2009-10-16 16:32:57 UTC (rev 4788) @@ -360,11 +360,11 @@ export always comment "Set for uncompressed image" end -define CONFIG_LB_MEM_TOPK +define CONFIG_RAMTOP format "%d" - default 2048 + default 2048*1024 export always - comment "Kilobytes of memory to initialized before executing code from RAM" + comment "Highest RAM that coreboot_ram will use" end define CONFIG_HAVE_OPTION_TABLE default 0 Modified: trunk/coreboot-v2/src/config/coreboot_ram.ld =================================================================== --- trunk/coreboot-v2/src/config/coreboot_ram.ld 2009-10-16 14:34:50 UTC (rev 4787) +++ trunk/coreboot-v2/src/config/coreboot_ram.ld 2009-10-16 16:32:57 UTC (rev 4788) @@ -103,8 +103,8 @@ _stack = .; .stack . : { /* Reserve a stack for each possible cpu */ - /* the stack for ap will be put after pgtbl in 1M to CONFIG_LB_MEM_TOPK range when VGA and ROM_RUN and CONFIG_LB_MEM_TOPK>1024*/ - . = ((CONFIG_CONSOLE_VGA || CONFIG_PCI_ROM_RUN)&&(CONFIG_RAMBASE<0x100000)&&(CONFIG_LB_MEM_TOPK>(0x100000>>10)) ) ? CONFIG_STACK_SIZE : (CONFIG_MAX_CPUS*CONFIG_STACK_SIZE); + /* the stack for ap will be put after pgtbl in 1M to CONFIG_RAMTOP range when VGA and ROM_RUN and CONFIG_RAMTOP>1M*/ + . = ((CONFIG_CONSOLE_VGA || CONFIG_PCI_ROM_RUN)&&(CONFIG_RAMBASE<0x100000)&&(CONFIG_RAMTOP>0x100000) ) ? CONFIG_STACK_SIZE : (CONFIG_MAX_CPUS*CONFIG_STACK_SIZE); } _estack = .; _heap = .; @@ -120,9 +120,9 @@ _ram_seg = _text; _eram_seg = _eheap; - _bogus = ASSERT( ( (_eram_seg>>10) < (CONFIG_LB_MEM_TOPK)) , "please increase CONFIG_LB_MEM_TOPK"); + _bogus = ASSERT( ( _eram_seg < (CONFIG_RAMTOP)) , "please increase CONFIG_RAMTOP"); - _bogus = ASSERT( !((CONFIG_CONSOLE_VGA || CONFIG_PCI_ROM_RUN) && ((_ram_seg<0xa0000) && (_eram_seg>0xa0000))) , "please increase CONFIG_LB_MEM_TOPK and if still fail, try to set CONFIG_RAMBASE more than 1M"); + _bogus = ASSERT( !((CONFIG_CONSOLE_VGA || CONFIG_PCI_ROM_RUN) && ((_ram_seg<0xa0000) && (_eram_seg>0xa0000))) , "please increase CONFIG_RAMTOP and if still fail, try to set CONFIG_RAMBASE more than 1M"); /DISCARD/ : { *(.comment) Modified: trunk/coreboot-v2/src/console/usbdebug_direct_console.c =================================================================== --- trunk/coreboot-v2/src/console/usbdebug_direct_console.c 2009-10-16 14:34:50 UTC (rev 4787) +++ trunk/coreboot-v2/src/console/usbdebug_direct_console.c 2009-10-16 16:32:57 UTC (rev 4788) @@ -53,7 +53,7 @@ * debug_info data structure to our version defined above. */ dbg_infox = (struct ehci_debug_info *) - ((CONFIG_LB_MEM_TOPK << 10) - sizeof(struct ehci_debug_info)); + ((CONFIG_RAMTOP) - sizeof(struct ehci_debug_info)); memcpy(&dbg_info, dbg_infox, sizeof(struct ehci_debug_info)); } Modified: trunk/coreboot-v2/src/cpu/amd/car/cache_as_ram.inc =================================================================== --- trunk/coreboot-v2/src/cpu/amd/car/cache_as_ram.inc 2009-10-16 14:34:50 UTC (rev 4787) +++ trunk/coreboot-v2/src/cpu/amd/car/cache_as_ram.inc 2009-10-16 16:32:57 UTC (rev 4788) @@ -246,7 +246,7 @@ /* enable memory access for first MBs using top_mem */ movl $TOP_MEM, %ecx xorl %edx, %edx - movl $(((CONFIG_LB_MEM_TOPK << 10) + TOP_MEM_MASK) & ~TOP_MEM_MASK) , %eax + movl $(((CONFIG_RAMTOP) + TOP_MEM_MASK) & ~TOP_MEM_MASK) , %eax wrmsr #endif /* CONFIG_USE_FAILOVER_IMAGE == 1*/ Modified: trunk/coreboot-v2/src/cpu/amd/car/clear_init_ram.c =================================================================== --- trunk/coreboot-v2/src/cpu/amd/car/clear_init_ram.c 2009-10-16 14:34:50 UTC (rev 4787) +++ trunk/coreboot-v2/src/cpu/amd/car/clear_init_ram.c 2009-10-16 16:32:57 UTC (rev 4788) @@ -9,15 +9,15 @@ #if CONFIG_HAVE_ACPI_RESUME == 1 /* clear only coreboot used region of memory. Note: this may break ECC enabled boards */ - clear_memory( CONFIG_RAMBASE, (CONFIG_LB_MEM_TOPK << 10) - CONFIG_RAMBASE - CONFIG_DCACHE_RAM_SIZE); + clear_memory( CONFIG_RAMBASE, (CONFIG_RAMTOP) - CONFIG_RAMBASE - CONFIG_DCACHE_RAM_SIZE); #else - clear_memory(0, ((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_SIZE)); + clear_memory(0, ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_SIZE)); #endif } /* be warned, this file will be used by core other than core 0/node 0 or core0/node0 when cpu_reset*/ static void set_init_ram_access(void) { - set_var_mtrr(0, 0x00000000, CONFIG_LB_MEM_TOPK << 10, MTRR_TYPE_WRBACK); + set_var_mtrr(0, 0x00000000, CONFIG_RAMTOP, MTRR_TYPE_WRBACK); } Modified: trunk/coreboot-v2/src/cpu/amd/car/post_cache_as_ram.c =================================================================== --- trunk/coreboot-v2/src/cpu/amd/car/post_cache_as_ram.c 2009-10-16 14:34:50 UTC (rev 4787) +++ trunk/coreboot-v2/src/cpu/amd/car/post_cache_as_ram.c 2009-10-16 16:32:57 UTC (rev 4788) @@ -56,13 +56,13 @@ print_debug_pcar("testx = ", testx); /* copy data from cache as ram to - ram need to set CONFIG_LB_MEM_TOPK to 2048 and use var mtrr instead. + ram need to set CONFIG_RAMTOP to 2M and use var mtrr instead. */ -#if CONFIG_LB_MEM_TOPK <= 1024 - #error "You need to set CONFIG_LB_MEM_TOPK greater than 1024" +#if CONFIG_RAMTOP <= 0x100000 + #error "You need to set CONFIG_RAMTOP greater than 1M" #endif - set_init_ram_access(); /* So we can access RAM from [1M, CONFIG_LB_MEM_TOPK) */ + set_init_ram_access(); /* So we can access RAM from [1M, CONFIG_RAMTOP) */ // dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x8000, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x7c00); print_debug("Copying data from cache to RAM -- switching to use RAM as stack... "); @@ -76,14 +76,14 @@ ); #endif - memcopy((void *)((CONFIG_LB_MEM_TOPK<<10)-CONFIG_DCACHE_RAM_SIZE), (void *)CONFIG_DCACHE_RAM_BASE, CONFIG_DCACHE_RAM_SIZE); //inline -// dump_mem((CONFIG_LB_MEM_TOPK<<10) - 0x8000, (CONFIG_LB_MEM_TOPK<<10) - 0x7c00); + memcopy((void *)((CONFIG_RAMTOP)-CONFIG_DCACHE_RAM_SIZE), (void *)CONFIG_DCACHE_RAM_BASE, CONFIG_DCACHE_RAM_SIZE); //inline +// dump_mem((CONFIG_RAMTOP) - 0x8000, (CONFIG_RAMTOP) - 0x7c00); __asm__ volatile ( /* set new esp */ /* before CONFIG_RAMBASE */ "subl %0, %%ebp\n\t" "subl %0, %%esp\n\t" - ::"a"( (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE)- (CONFIG_LB_MEM_TOPK<<10) ) + ::"a"( (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE)- (CONFIG_RAMTOP) ) ); // We need to push %eax to the stack (CAR) before copy stack and pop it later after copy stack and change esp #if 0 __asm__ volatile ( @@ -102,10 +102,10 @@ disable_cache_as_ram_bsp(); print_debug("Clearing initial memory region: "); - clear_init_ram(); //except the range from [(CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_SIZE, (CONFIG_LB_MEM_TOPK<<10)) + clear_init_ram(); //except the range from [(CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_SIZE, (CONFIG_RAMTOP)) print_debug("Done\r\n"); -// dump_mem((CONFIG_LB_MEM_TOPK<<10) - 0x8000, (CONFIG_LB_MEM_TOPK<<10) - 0x7c00); +// dump_mem((CONFIG_RAMTOP) - 0x8000, (CONFIG_RAMTOP) - 0x7c00); #ifndef CONFIG_MEM_TRAIN_SEQ #define CONFIG_MEM_TRAIN_SEQ 0 @@ -113,7 +113,7 @@ set_sysinfo_in_ram(1); // So other core0 could start to train mem #if CONFIG_MEM_TRAIN_SEQ == 1 -// struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); +// struct sys_info *sysinfox = ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // wait for ap memory to trained // wait_all_core0_mem_trained(sysinfox); // moved to lapic_init_cpus.c Modified: trunk/coreboot-v2/src/cpu/amd/model_fxx/model_fxx_init.c =================================================================== --- trunk/coreboot-v2/src/cpu/amd/model_fxx/model_fxx_init.c 2009-10-16 14:34:50 UTC (rev 4787) +++ trunk/coreboot-v2/src/cpu/amd/model_fxx/model_fxx_init.c 2009-10-16 16:32:57 UTC (rev 4788) @@ -33,7 +33,7 @@ void cpus_ready_for_init(void) { #if CONFIG_MEM_TRAIN_SEQ == 1 - struct sys_info *sysinfox = (struct sys_info *)((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfox = (struct sys_info *)((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // wait for ap memory to trained wait_all_core0_mem_trained(sysinfox); #endif @@ -182,7 +182,7 @@ msr.lo = 0x00000000 | MTRR_TYPE_WRBACK; wrmsr(MTRRphysBase_MSR(0), msr); msr.hi = 0x000000ff; - msr.lo = ~((CONFIG_LB_MEM_TOPK << 10) - 1) | 0x800; + msr.lo = ~((CONFIG_RAMTOP) - 1) | 0x800; wrmsr(MTRRphysMask_MSR(0), msr); /* Set the default type to write combining */ @@ -308,8 +308,8 @@ /* Don't start too early */ begink = startk; - if (begink < CONFIG_LB_MEM_TOPK) { - begink = CONFIG_LB_MEM_TOPK; + if (begink < (CONFIG_RAMTOP >> 10)) { + begink = (CONFIG_RAMTOP >>10); } printk_debug("Clearing memory %luK - %luK: ", begink, endk); Modified: trunk/coreboot-v2/src/cpu/amd/mtrr/amd_earlymtrr.c =================================================================== --- trunk/coreboot-v2/src/cpu/amd/mtrr/amd_earlymtrr.c 2009-10-16 14:34:50 UTC (rev 4787) +++ trunk/coreboot-v2/src/cpu/amd/mtrr/amd_earlymtrr.c 2009-10-16 16:32:57 UTC (rev 4788) @@ -38,7 +38,7 @@ /* Enable memory access for 0 - 1MB using top_mem */ msr.hi = 0; - msr.lo = (((CONFIG_LB_MEM_TOPK << 10) + TOP_MEM_MASK) & ~TOP_MEM_MASK); + msr.lo = (((CONFIG_RAMTOP) + TOP_MEM_MASK) & ~TOP_MEM_MASK); wrmsr(TOP_MEM, msr); #if defined(CONFIG_XIP_ROM_SIZE) Modified: trunk/coreboot-v2/src/cpu/x86/lapic/lapic_cpu_init.c =================================================================== --- trunk/coreboot-v2/src/cpu/x86/lapic/lapic_cpu_init.c 2009-10-16 14:34:50 UTC (rev 4787) +++ trunk/coreboot-v2/src/cpu/x86/lapic/lapic_cpu_init.c 2009-10-16 16:32:57 UTC (rev 4788) @@ -246,17 +246,17 @@ index = ++last_cpu_index; /* Find end of the new processors stack */ -#if (CONFIG_LB_MEM_TOPK>1024) && (CONFIG_RAMBASE < 0x100000) && ((CONFIG_CONSOLE_VGA==1) || (CONFIG_PCI_ROM_RUN == 1)) +#if (CONFIG_RAMTOP>0x100000) && (CONFIG_RAMBASE < 0x100000) && ((CONFIG_CONSOLE_VGA==1) || (CONFIG_PCI_ROM_RUN == 1)) if(index<1) { // only keep bsp on low stack_end = ((unsigned long)_estack) - (CONFIG_STACK_SIZE*index) - sizeof(struct cpu_info); } else { // for all APs, let use stack after pgtbl, 20480 is the pgtbl size for every cpu stack_end = 0x100000+(20480 + CONFIG_STACK_SIZE)*CONFIG_MAX_CPUS - (CONFIG_STACK_SIZE*index); -#if (0x100000+(20480 + CONFIG_STACK_SIZE)*CONFIG_MAX_CPUS) > (CONFIG_LB_MEM_TOPK<<10) - #warning "We may need to increase CONFIG_LB_MEM_TOPK, it need to be more than (0x100000+(20480 + CONFIG_STACK_SIZE)*CONFIG_MAX_CPUS)\n" +#if (0x100000+(20480 + CONFIG_STACK_SIZE)*CONFIG_MAX_CPUS) > (CONFIG_RAMTOP) + #warning "We may need to increase CONFIG_RAMTOP, it need to be more than (0x100000+(20480 + CONFIG_STACK_SIZE)*CONFIG_MAX_CPUS)\n" #endif - if(stack_end > (CONFIG_LB_MEM_TOPK<<10)) { - printk_debug("start_cpu: Please increase the CONFIG_LB_MEM_TOPK more than %luK\n", stack_end>>10); + if(stack_end > (CONFIG_RAMTOP)) { + printk_debug("start_cpu: Please increase the CONFIG_RAMTOP more than %luK\n", stack_end); die("Can not go on\n"); } stack_end -= sizeof(struct cpu_info); Modified: trunk/coreboot-v2/src/cpu/x86/mtrr/earlymtrr.c =================================================================== --- trunk/coreboot-v2/src/cpu/x86/mtrr/earlymtrr.c 2009-10-16 14:34:50 UTC (rev 4787) +++ trunk/coreboot-v2/src/cpu/x86/mtrr/earlymtrr.c 2009-10-16 16:32:57 UTC (rev 4788) @@ -11,8 +11,8 @@ #if defined(CONFIG_XIP_ROM_BASE) && !defined(CONFIG_XIP_ROM_SIZE) # error "CONFIG_XIP_ROM_BASE without CONFIG_XIP_ROM_SIZE" #endif -#if !defined(CONFIG_LB_MEM_TOPK) -# error "CONFIG_LB_MEM_TOPK not defined" +#if !defined(CONFIG_RAMTOP) +# error "CONFIG_RAMTOP not defined" #endif #if defined(CONFIG_XIP_ROM_SIZE) && ((CONFIG_XIP_ROM_SIZE & (CONFIG_XIP_ROM_SIZE -1)) != 0) @@ -22,8 +22,8 @@ # error "CONFIG_XIP_ROM_BASE is not a multiple of CONFIG_XIP_ROM_SIZE" #endif -#if (CONFIG_LB_MEM_TOPK & (CONFIG_LB_MEM_TOPK -1)) != 0 -# error "CONFIG_LB_MEM_TOPK must be a power of 2" +#if (CONFIG_RAMTOP & (CONFIG_RAMTOP -1)) != 0 +# error "CONFIG_RAMTOP must be a power of 2" #endif static void disable_var_mtrr(unsigned reg) @@ -75,7 +75,7 @@ { /* Enable caching for 0 - 1MB using variable mtrr */ disable_cache(); - set_var_mtrr(0, 0x00000000, CONFIG_LB_MEM_TOPK << 10, type); + set_var_mtrr(0, 0x00000000, CONFIG_RAMTOP, type); enable_cache(); } Modified: trunk/coreboot-v2/src/cpu/x86/pae/pgtbl.c =================================================================== --- trunk/coreboot-v2/src/cpu/x86/pae/pgtbl.c 2009-10-16 14:34:50 UTC (rev 4787) +++ trunk/coreboot-v2/src/cpu/x86/pae/pgtbl.c 2009-10-16 16:32:57 UTC (rev 4788) @@ -54,19 +54,19 @@ struct pde pdp[512]; } __attribute__ ((packed)); -#if (CONFIG_LB_MEM_TOPK>1024) && (CONFIG_RAMBASE<0x100000) && ((CONFIG_CONSOLE_VGA==1) || (CONFIG_PCI_ROM_RUN == 1)) +#if (CONFIG_RAMTOP>0x100000) && (CONFIG_RAMBASE<0x100000) && ((CONFIG_CONSOLE_VGA==1) || (CONFIG_PCI_ROM_RUN == 1)) /* pgtbl is too big, so use last one 1M before CONFIG_LB_MEM_TOP, otherwise for 8 way dual core with vga support will push stack and heap cross 0xa0000, - and that region need to be used as vga font buffer. Please make sure set CONFIG_LB_MEM_TOPK=2048 in MB Config + and that region need to be used as vga font buffer. Please make sure set CONFIG_RAMTOP=0x200000 in MB Config */ struct pg_table *pgtbl = (struct pg_table*)0x100000; //1M unsigned x_end = 0x100000 + sizeof(struct pg_table) * CONFIG_MAX_CPUS; -#if (0x100000+20480*CONFIG_MAX_CPUS) > (CONFIG_LB_MEM_TOPK<<10) - #warning "We may need to increase CONFIG_LB_MEM_TOPK, it need to be more than (0x100000+20480*CONFIG_MAX_CPUS)\n" +#if (0x100000+20480*CONFIG_MAX_CPUS) > (CONFIG_RAMTOP) + #warning "We may need to increase CONFIG_RAMTOP, it need to be more than (0x100000+20480*CONFIG_MAX_CPUS)\n" #endif - if(x_end > (CONFIG_LB_MEM_TOPK<<10)) { - printk_debug("map_2M_page: Please increase the CONFIG_LB_MEM_TOPK more than %dK\n", x_end>>10); + if(x_end > (CONFIG_RAMTOP)) { + printk_debug("map_2M_page: Please increase the CONFIG_RAMTOP more than %dK\n", x_end); die("Can not go on"); } #else Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Options.lb 2009-10-16 14:34:50 UTC (rev 4787) +++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Options.lb 2009-10-16 16:32:57 UTC (rev 4788) @@ -80,7 +80,7 @@ uses CONFIG_PCI_64BIT_PREF_MEM -uses CONFIG_LB_MEM_TOPK +uses CONFIG_RAMTOP uses CONFIG_AP_CODE_IN_CAR @@ -107,7 +107,7 @@ default CONFIG_FAILOVER_SIZE=0x01000 #more 1M for pgtbl -default CONFIG_LB_MEM_TOPK=2048 +default CONFIG_RAMTOP=2048*1024 ## ## Build code for the fallback boot Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/apc_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/apc_auto.c 2009-10-16 14:34:50 UTC (rev 4787) +++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/apc_auto.c 2009-10-16 16:32:57 UTC (rev 4788) @@ -75,7 +75,7 @@ void hardwaremain(int ret_addr) { struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE - struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM + struct sys_info *sysinfox = ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM struct node_core_id id; Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig 2009-10-16 14:34:50 UTC (rev 4787) +++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig 2009-10-16 16:32:57 UTC (rev 4788) @@ -95,9 +95,9 @@ default "mc_patch_01000095.h" depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10 -config LB_MEM_TOPK +config RAMTOP hex - default 0x4000 + default 0x1000000 depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10 config HEAP_SIZE Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb 2009-10-16 14:34:50 UTC (rev 4787) +++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb 2009-10-16 16:32:57 UTC (rev 4788) @@ -98,7 +98,7 @@ uses CONFIG_PCI_64BIT_PREF_MEM -uses CONFIG_LB_MEM_TOPK +uses CONFIG_RAMTOP uses CONFIG_PCI_BUS_SEGN_BITS @@ -135,7 +135,7 @@ #more 1M for pgtbl #if there is RAM on node0, we need to set it to 32M, otherwise can not access CAR on node0, and RAM on node1 at same time. -default CONFIG_LB_MEM_TOPK=16384 +default CONFIG_RAMTOP=16384*1024 ## ## Build code for the fallback boot Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/apc_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/apc_auto.c 2009-10-16 14:34:50 UTC (rev 4787) +++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/apc_auto.c 2009-10-16 16:32:57 UTC (rev 4788) @@ -74,7 +74,7 @@ void hardwaremain(int ret_addr) { struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE - struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM + struct sys_info *sysinfox = ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM struct node_core_id id; Modified: trunk/coreboot-v2/src/mainboard/asus/a8n_e/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/a8n_e/Options.lb 2009-10-16 14:34:50 UTC (rev 4787) +++ trunk/coreboot-v2/src/mainboard/asus/a8n_e/Options.lb 2009-10-16 16:32:57 UTC (rev 4788) @@ -93,7 +93,6 @@ uses CONFIG_HT_CHAIN_END_UNITID_BASE uses CONFIG_SB_HT_CHAIN_ON_BUS0 uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY -uses CONFIG_LB_MEM_TOPK uses CONFIG_USE_PRINTK_IN_CAR default CONFIG_ROM_SIZE = 512 * 1024 Modified: trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/Options.lb 2009-10-16 14:34:50 UTC (rev 4787) +++ trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/Options.lb 2009-10-16 16:32:57 UTC (rev 4788) @@ -41,7 +41,7 @@ uses CONFIG_STACK_SIZE uses CONFIG_HEAP_SIZE # uses CONFIG_USE_OPTION_TABLE -# uses CONFIG_LB_MEM_TOPK +# uses CONFIG_RAMTOP uses CONFIG_GENERATE_ACPI_TABLES uses CONFIG_HAVE_ACPI_RESUME uses CONFIG_LB_CKS_RANGE_START @@ -147,7 +147,7 @@ default CONFIG_STACK_SIZE = 8 * 1024 default CONFIG_HEAP_SIZE = 256 * 1024 # More 1M for pgtbl. -# default CONFIG_LB_MEM_TOPK = 2048 +# default CONFIG_RAMTOP = 2048*1024 default CONFIG_RAMBASE = 0x00004000 # default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE default CONFIG_ROM_PAYLOAD = 1 Modified: trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/Options.lb 2009-10-16 14:34:50 UTC (rev 4787) +++ trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/Options.lb 2009-10-16 16:32:57 UTC (rev 4788) @@ -41,7 +41,7 @@ uses CONFIG_STACK_SIZE uses CONFIG_HEAP_SIZE uses CONFIG_USE_OPTION_TABLE -uses CONFIG_LB_MEM_TOPK +uses CONFIG_RAMTOP uses CONFIG_GENERATE_ACPI_TABLES uses CONFIG_HAVE_MAINBOARD_RESOURCES uses CONFIG_HAVE_ACPI_RESUME @@ -151,7 +151,7 @@ default CONFIG_STACK_SIZE = 8 * 1024 default CONFIG_HEAP_SIZE = 256 * 1024 # More 1M for pgtbl. -default CONFIG_LB_MEM_TOPK = 32768 +default CONFIG_RAMTOP = 32768*1024 # to 1MB default CONFIG_RAMBASE = 0x1F00000 default CONFIG_USE_OPTION_TABLE = 0 Modified: trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/mainboard.c =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/mainboard.c 2009-10-16 14:34:50 UTC (rev 4787) +++ trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/mainboard.c 2009-10-16 16:32:57 UTC (rev 4788) @@ -40,7 +40,7 @@ #if CONFIG_HAVE_ACPI_RESUME == 1 lb_add_memory_range(mem, LB_MEM_RESERVED, - CONFIG_RAMBASE, ((CONFIG_LB_MEM_TOPK<<10) - CONFIG_RAMBASE)); + CONFIG_RAMBASE, ((CONFIG_RAMTOP) - CONFIG_RAMBASE)); lb_add_memory_range(mem, LB_MEM_RESERVED, CONFIG_DCACHE_RAM_BASE, CONFIG_DCACHE_RAM_SIZE); #endif Modified: trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/Options.lb 2009-10-16 14:34:50 UTC (rev 4787) +++ trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/Options.lb 2009-10-16 16:32:57 UTC (rev 4788) @@ -105,7 +105,7 @@ uses CONFIG_PCI_64BIT_PREF_MEM -uses CONFIG_LB_MEM_TOPK +uses CONFIG_RAMTOP uses CONFIG_AP_CODE_IN_CAR @@ -135,7 +135,7 @@ default CONFIG_FAILOVER_SIZE=0x01000 #more 1M for pgtbl -default CONFIG_LB_MEM_TOPK=2048 +default CONFIG_RAMTOP=2048*1024 ## ## Build code for the fallback boot Modified: trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/apc_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/apc_auto.c 2009-10-16 14:34:50 UTC (rev 4787) +++ trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/apc_auto.c 2009-10-16 16:32:57 UTC (rev 4788) @@ -89,7 +89,7 @@ void hardwaremain(int ret_addr) { struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE - struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM + struct sys_info *sysinfox = ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM struct node_core_id id; Modified: trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Options.lb 2009-10-16 14:34:50 UTC (rev 4787) +++ trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Options.lb 2009-10-16 16:32:57 UTC (rev 4788) @@ -105,7 +105,7 @@ uses CONFIG_PCI_64BIT_PREF_MEM -uses CONFIG_LB_MEM_TOPK +uses CONFIG_RAMTOP uses CONFIG_AP_CODE_IN_CAR @@ -136,7 +136,7 @@ default CONFIG_FAILOVER_SIZE=0x01000 #more 1M for pgtbl -default CONFIG_LB_MEM_TOPK=2048 +default CONFIG_RAMTOP=2048*1024 ## ## Set-up automatic fan control Modified: trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/apc_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/apc_auto.c 2009-10-16 14:34:50 UTC (rev 4787) +++ trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/apc_auto.c 2009-10-16 16:32:57 UTC (rev 4788) @@ -87,7 +87,7 @@ void hardwaremain(int ret_addr) { struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE - struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM + struct sys_info *sysinfox = ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM struct node_core_id id; Modified: trunk/coreboot-v2/src/mainboard/hp/dl145_g3/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/hp/dl145_g3/Options.lb 2009-10-16 14:34:50 UTC (rev 4787) +++ trunk/coreboot-v2/src/mainboard/hp/dl145_g3/Options.lb 2009-10-16 16:32:57 UTC (rev 4788) @@ -102,7 +102,7 @@ uses CONFIG_PCI_64BIT_PREF_MEM -uses CONFIG_LB_MEM_TOPK +uses CONFIG_RAMTOP uses CONFIG_USE_PRINTK_IN_CAR @@ -121,7 +121,7 @@ default CONFIG_FALLBACK_SIZE=CONFIG_ROM_IMAGE_SIZE #more 1M for pgtbl -default CONFIG_LB_MEM_TOPK=2048 +default CONFIG_RAMTOP=2048*1024 ## ## Build code for the fallback boot Modified: trunk/coreboot-v2/src/mainboard/intel/truxton/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/intel/truxton/Options.lb 2009-10-16 14:34:50 UTC (rev 4787) +++ trunk/coreboot-v2/src/mainboard/intel/truxton/Options.lb 2009-10-16 16:32:57 UTC (rev 4788) @@ -35,7 +35,7 @@ uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_LB_MEM_TOPK +uses CONFIG_RAMTOP uses CONFIG_ROMBASE uses CONFIG_XIP_ROM_SIZE uses CONFIG_XIP_ROM_BASE @@ -157,9 +157,9 @@ default CONFIG_RAMBASE=0x00100000 ## -## in order to have coreboot running at 0x100000, TOPK has to be set +## in order to have coreboot running at 0x100000, RAMTOP has to be set ## -default CONFIG_LB_MEM_TOPK = 2*1024*1024 +default CONFIG_RAMTOP = 2*1024*1024 ## ## Load the payload from the ROM Modified: trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/Options.lb 2009-10-16 14:34:50 UTC (rev 4787) +++ trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/Options.lb 2009-10-16 16:32:57 UTC (rev 4788) @@ -80,7 +80,7 @@ uses CONFIG_PCI_64BIT_PREF_MEM -uses CONFIG_LB_MEM_TOPK +uses CONFIG_RAMTOP uses CONFIG_AP_CODE_IN_CAR @@ -109,7 +109,7 @@ default CONFIG_FAILOVER_SIZE=0x02000 #more 1M for pgtbl -default CONFIG_LB_MEM_TOPK=2048 +default CONFIG_RAMTOP=2048*1024 ## ## Build code for the fallback boot Modified: trunk/coreboot-v2/src/mainboard/msi/ms7135/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms7135/Options.lb 2009-10-16 14:34:50 UTC (rev 4787) +++ trunk/coreboot-v2/src/mainboard/msi/ms7135/Options.lb 2009-10-16 16:32:57 UTC (rev 4788) @@ -99,9 +99,6 @@ uses CONFIG_SB_HT_CHAIN_ON_BUS0 uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY -uses CONFIG_LB_MEM_TOPK - - ## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. ## ---> 512 Kbytes default CONFIG_ROM_SIZE=(512*1024) Modified: trunk/coreboot-v2/src/mainboard/msi/ms7260/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms7260/Options.lb 2009-10-16 14:34:50 UTC (rev 4787) +++ trunk/coreboot-v2/src/mainboard/msi/ms7260/Options.lb 2009-10-16 16:32:57 UTC (rev 4788) @@ -91,7 +91,7 @@ uses CONFIG_APIC_ID_OFFSET uses CONFIG_LIFT_BSP_APIC_ID uses CONFIG_PCI_64BIT_PREF_MEM -uses CONFIG_LB_MEM_TOPK +uses CONFIG_RAMTOP uses CONFIG_AP_CODE_IN_CAR uses CONFIG_MEM_TRAIN_SEQ uses CONFIG_WAIT_BEFORE_CPUS_INIT @@ -100,7 +100,7 @@ default CONFIG_ROM_SIZE = 512 * 1024 default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE default CONFIG_FAILOVER_SIZE = 4 * 1024 -default CONFIG_LB_MEM_TOPK = 2048 # 1MB more for pgtbl. +default CONFIG_RAMTOP = 2048*1024 # 1MB more for pgtbl. default CONFIG_HAVE_FALLBACK_BOOT = 1 default CONFIG_HAVE_FAILOVER_BOOT = 1 default CONFIG_HAVE_HARD_RESET = 1 Modified: trunk/coreboot-v2/src/mainboard/msi/ms7260/apc_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms7260/apc_auto.c 2009-10-16 14:34:50 UTC (rev 4787) +++ trunk/coreboot-v2/src/mainboard/msi/ms7260/apc_auto.c 2009-10-16 16:32:57 UTC (rev 4788) @@ -63,7 +63,7 @@ { struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); /* in CACHE */ - struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK << 10) - + struct sys_info *sysinfox = ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); /* in RAM */ struct node_core_id id; Modified: trunk/coreboot-v2/src/mainboard/msi/ms9185/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms9185/Options.lb 2009-10-16 14:34:50 UTC (rev 4787) +++ trunk/coreboot-v2/src/mainboard/msi/ms9185/Options.lb 2009-10-16 16:32:57 UTC (rev 4788) @@ -101,7 +101,7 @@ uses CONFIG_PCI_64BIT_PREF_MEM -uses CONFIG_LB_MEM_TOPK +uses CONFIG_RAMTOP uses CONFIG_USE_PRINTK_IN_CAR ### @@ -118,7 +118,7 @@ default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE #more 1M for pgtbl -default CONFIG_LB_MEM_TOPK=2048 +default CONFIG_RAMTOP=2048*1024 ## ## Build code for the fallback boot Modified: trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/Options.lb 2009-10-16 14:34:50 UTC (rev 4787) +++ trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/Options.lb 2009-10-16 16:32:57 UTC (rev 4788) @@ -103,7 +103,7 @@ uses CONFIG_PCI_64BIT_PREF_MEM -uses CONFIG_LB_MEM_TOPK +uses CONFIG_RAMTOP uses CONFIG_AP_CODE_IN_CAR @@ -133,7 +133,7 @@ default CONFIG_FAILOVER_SIZE=0x01000 #more 1M for pgtbl -default CONFIG_LB_MEM_TOPK=2048 +default CONFIG_RAMTOP=2048*1024 ## ## Build code for the fallback boot Modified: trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/apc_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/apc_auto.c 2009-10-16 14:34:50 UTC (rev 4787) +++ trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/apc_auto.c 2009-10-16 16:32:57 UTC (rev 4788) @@ -87,7 +87,7 @@ void hardwaremain(int ret_addr) { struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE - struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM + struct sys_info *sysinfox = ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM struct node_core_id id; Modified: trunk/coreboot-v2/src/mainboard/supermicro/h8dme/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/h8dme/Options.lb 2009-10-16 14:34:50 UTC (rev 4787) +++ trunk/coreboot-v2/src/mainboard/supermicro/h8dme/Options.lb 2009-10-16 16:32:57 UTC (rev 4788) @@ -104,7 +104,7 @@ uses CONFIG_PCI_64BIT_PREF_MEM -uses CONFIG_LB_MEM_TOPK +uses CONFIG_RAMTOP uses CONFIG_AP_CODE_IN_CAR @@ -137,7 +137,7 @@ default CONFIG_FAILOVER_SIZE=0x01000 #more 1M for pgtbl -default CONFIG_LB_MEM_TOPK=2048 +default CONFIG_RAMTOP=2048*1024 ## ## Build code for the fallback boot Modified: trunk/coreboot-v2/src/mainboard/supermicro/h8dme/apc_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/h8dme/apc_auto.c 2009-10-16 14:34:50 UTC (rev 4787) +++ trunk/coreboot-v2/src/mainboard/supermicro/h8dme/apc_auto.c 2009-10-16 16:32:57 UTC (rev 4788) @@ -95,7 +95,7 @@ void hardwaremain(int ret_addr) { struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE - struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM + struct sys_info *sysinfox = ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM struct node_core_id id; Modified: trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/Options.lb 2009-10-16 14:34:50 UTC (rev 4787) +++ trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/Options.lb 2009-10-16 16:32:57 UTC (rev 4788) @@ -102,7 +102,7 @@ uses CONFIG_PCI_64BIT_PREF_MEM -uses CONFIG_LB_MEM_TOPK +uses CONFIG_RAMTOP uses CONFIG_AP_CODE_IN_CAR @@ -130,7 +130,7 @@ default CONFIG_FAILOVER_SIZE=0x01000 #more 1M for pgtbl -default CONFIG_LB_MEM_TOPK=2048 +default CONFIG_RAMTOP=2048*1024 ## ## Build code for the fallback boot Modified: trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/apc_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/apc_auto.c 2009-10-16 14:34:50 UTC (rev 4787) +++ trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/apc_auto.c 2009-10-16 16:32:57 UTC (rev 4788) @@ -95,7 +95,7 @@ void hardwaremain(int ret_addr) { struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE - struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM + struct sys_info *sysinfox = ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM struct node_core_id id; Modified: trunk/coreboot-v2/src/mainboard/supermicro/h8dmr_fam10/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/h8dmr_fam10/Options.lb 2009-10-16 14:34:50 UTC (rev 4787) +++ trunk/coreboot-v2/src/mainboard/supermicro/h8dmr_fam10/Options.lb 2009-10-16 16:32:57 UTC (rev 4788) @@ -99,7 +99,7 @@ uses CONFIG_PCI_64BIT_PREF_MEM -uses CONFIG_LB_MEM_TOPK +uses CONFIG_RAMTOP uses CONFIG_UNCOMPRESSED @@ -132,7 +132,7 @@ default CONFIG_FAILOVER_SIZE=0x02000 #more 1M for pgtbl -default CONFIG_LB_MEM_TOPK=16384 +default CONFIG_RAMTOP=16384*1024 ## ## Build code for the fallback boot Modified: trunk/coreboot-v2/src/mainboard/supermicro/h8dmr_fam10/apc_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/h8dmr_fam10/apc_auto.c 2009-10-16 14:34:50 UTC (rev 4787) +++ trunk/coreboot-v2/src/mainboard/supermicro/h8dmr_fam10/apc_auto.c 2009-10-16 16:32:57 UTC (rev 4788) @@ -95,7 +95,7 @@ void hardwaremain(int ret_addr) { struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE - struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM + struct sys_info *sysinfox = ((CONFIG_RAMTOP) - DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM struct node_core_id id; Modified: trunk/coreboot-v2/src/mainboard/tyan/s2885/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2885/Options.lb 2009-10-16 14:34:50 UTC (rev 4787) +++ trunk/coreboot-v2/src/mainboard/tyan/s2885/Options.lb 2009-10-16 16:32:57 UTC (rev 4788) @@ -68,8 +68,6 @@ uses CONFIG_SB_HT_CHAIN_ON_BUS0 uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY -uses CONFIG_LB_MEM_TOPK - ### ### Build options ### Modified: trunk/coreboot-v2/src/mainboard/tyan/s2891/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2891/Options.lb 2009-10-16 14:34:50 UTC (rev 4787) +++ trunk/coreboot-v2/src/mainboard/tyan/s2891/Options.lb 2009-10-16 16:32:57 UTC (rev 4788) @@ -77,8 +77,6 @@ uses CONFIG_SB_HT_CHAIN_ON_BUS0 uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY -uses CONFIG_LB_MEM_TOPK - ## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. default CONFIG_ROM_SIZE=512*1024 Modified: trunk/coreboot-v2/src/mainboard/tyan/s2892/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2892/Options.lb 2009-10-16 14:34:50 UTC (rev 4787) +++ trunk/coreboot-v2/src/mainboard/tyan/s2892/Options.lb 2009-10-16 16:32:57 UTC (rev 4788) @@ -71,8 +71,6 @@ uses CONFIG_SB_HT_CHAIN_ON_BUS0 uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY -uses CONFIG_LB_MEM_TOPK - ## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. default CONFIG_ROM_SIZE=1024*1024 Modified: trunk/coreboot-v2/src/mainboard/tyan/s2895/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2895/Options.lb 2009-10-16 14:34:50 UTC (rev 4787) +++ trunk/coreboot-v2/src/mainboard/tyan/s2895/Options.lb 2009-10-16 16:32:57 UTC (rev 4788) @@ -80,7 +80,7 @@ uses CONFIG_SB_HT_CHAIN_ON_BUS0 uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY -uses CONFIG_LB_MEM_TOPK +uses CONFIG_RAMTOP ## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. default CONFIG_ROM_SIZE=1024*1024 @@ -95,7 +95,7 @@ default CONFIG_FAILOVER_SIZE=0x01000 #more 1M for pgtbl -default CONFIG_LB_MEM_TOPK=2048 +default CONFIG_RAMTOP=2048*1024 ## ## Build code for the fallback boot Modified: trunk/coreboot-v2/src/mainboard/tyan/s2912/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2912/Options.lb 2009-10-16 14:34:50 UTC (rev 4787) +++ trunk/coreboot-v2/src/mainboard/tyan/s2912/Options.lb 2009-10-16 16:32:57 UTC (rev 4788) @@ -103,7 +103,7 @@ uses CONFIG_PCI_64BIT_PREF_MEM -uses CONFIG_LB_MEM_TOPK +uses CONFIG_RAMTOP uses CONFIG_AP_CODE_IN_CAR @@ -133,7 +133,7 @@ default CONFIG_FAILOVER_SIZE=0x01000 #more 1M for pgtbl -default CONFIG_LB_MEM_TOPK=2048 +default CONFIG_RAMTOP=2048*1024 ## ## Build code for the fallback boot Modified: trunk/coreboot-v2/src/mainboard/tyan/s2912/apc_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2912/apc_auto.c 2009-10-16 14:34:50 UTC (rev 4787) +++ trunk/coreboot-v2/src/mainboard/tyan/s2912/apc_auto.c 2009-10-16 16:32:57 UTC (rev 4788) @@ -76,7 +76,7 @@ void hardwaremain(int ret_addr) { struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE - struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM + struct sys_info *sysinfox = ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM struct node_core_id id; Modified: trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/Options.lb 2009-10-16 14:34:50 UTC (rev 4787) +++ trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/Options.lb 2009-10-16 16:32:57 UTC (rev 4788) @@ -101,7 +101,7 @@ uses CONFIG_PCI_64BIT_PREF_MEM -uses CONFIG_LB_MEM_TOPK +uses CONFIG_RAMTOP uses CONFIG_PCI_BUS_SEGN_BITS @@ -135,7 +135,7 @@ default CONFIG_FAILOVER_SIZE=0x01000 #more 1M for pgtbl -default CONFIG_LB_MEM_TOPK=16384 +default CONFIG_RAMTOP=16384*1024 ## ## Build code for the fallback boot Modified: trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/apc_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/apc_auto.c 2009-10-16 14:34:50 UTC (rev 4787) +++ trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/apc_auto.c 2009-10-16 16:32:57 UTC (rev 4788) @@ -76,7 +76,7 @@ void hardwaremain(int ret_addr) { struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE - struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM + struct sys_info *sysinfox = ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM struct node_core_id id; Modified: trunk/coreboot-v2/src/mainboard/via/epia-n/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/via/epia-n/Options.lb 2009-10-16 14:34:50 UTC (rev 4787) +++ trunk/coreboot-v2/src/mainboard/via/epia-n/Options.lb 2009-10-16 16:32:57 UTC (rev 4788) @@ -34,7 +34,7 @@ uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION uses CONFIG_ARCH -uses CONFIG_LB_MEM_TOPK +uses CONFIG_RAMTOP uses CONFIG_FALLBACK_SIZE uses CONFIG_STACK_SIZE uses CONFIG_HEAP_SIZE @@ -73,7 +73,7 @@ uses CONFIG_HAVE_MAINBOARD_RESOURCES default CONFIG_EPIA_VT8237R_INIT = 1 -#default CONFIG_LB_MEM_TOPK = 4 * 1024 +#default CONFIG_RAMTOP = 4 * 1024*1024 default CONFIG_ROM_SIZE = 512 * 1024 default CONFIG_COMPRESS = 1 default CONFIG_IOAPIC = 1 Modified: trunk/coreboot-v2/src/northbridge/amd/amdfam10/amdfam10_acpi.c =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdfam10/amdfam10_acpi.c 2009-10-16 14:34:50 UTC (rev 4787) +++ trunk/coreboot-v2/src/northbridge/amd/amdfam10/amdfam10_acpi.c 2009-10-16 16:32:57 UTC (rev 4788) @@ -134,7 +134,7 @@ /* fill the first 8 byte with that num */ /* fill the next num*num byte with distance, local is 10, 1 hop mean 20, and 2 hop with 30.... */ - struct sys_info *sysinfox = (struct sys_info *)((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfox = (struct sys_info *)((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); u8 *ln = sysinfox->ln; Modified: trunk/coreboot-v2/src/northbridge/amd/amdfam10/northbridge.c =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdfam10/northbridge.c 2009-10-16 14:34:50 UTC (rev 4787) +++ trunk/coreboot-v2/src/northbridge/amd/amdfam10/northbridge.c 2009-10-16 16:32:57 UTC (rev 4788) @@ -806,7 +806,7 @@ u32 hole_sizek; u32 one_DCT; - struct sys_info *sysinfox = (struct sys_info *)((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM + struct sys_info *sysinfox = (struct sys_info *)((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM struct mem_info *meminfo; meminfo = &sysinfox->meminfo[i]; @@ -1065,7 +1065,7 @@ #if CONFIG_AMDMCT == 0 #if CONFIG_HW_MEM_HOLE_SIZEK != 0 if(reset_memhole) { - struct sys_info *sysinfox = (struct sys_info *)((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM + struct sys_info *sysinfox = (struct sys_info *)((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM struct mem_info *meminfo; meminfo = &sysinfox->meminfo[i]; sizek += hoist_memory(mmio_basek,i, get_one_DCT(meminfo), sysconf.nodes); Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit.c =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit.c 2009-10-16 14:34:50 UTC (rev 4787) +++ trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit.c 2009-10-16 16:32:57 UTC (rev 4788) @@ -11,8 +11,8 @@ #include "raminit.h" #include "amdk8.h" -#if (CONFIG_LB_MEM_TOPK & (CONFIG_LB_MEM_TOPK -1)) != 0 -# error "CONFIG_LB_MEM_TOPK must be a power of 2" +#if (CONFIG_RAMTOP & (CONFIG_RAMTOP -1)) != 0 +# error "CONFIG_RAMTOP must be a power of 2" #endif #ifndef QRANK_DIMM_SUPPORT Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit_f.c =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit_f.c 2009-10-16 14:34:50 UTC (rev 4787) +++ trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit_f.c 2009-10-16 16:32:57 UTC (rev 4788) @@ -48,8 +48,8 @@ #endif -#if (CONFIG_LB_MEM_TOPK & (CONFIG_LB_MEM_TOPK -1)) != 0 -# error "CONFIG_LB_MEM_TOPK must be a power of 2" +#if (CONFIG_RAMTOP & (CONFIG_RAMTOP -1)) != 0 +# error "CONFIG_RAMTOP must be a power of 2" #endif #include "amdk8_f_pci.c" Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit_f_dqs.c =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit_f_dqs.c 2009-10-16 14:34:50 UTC (rev 4787) +++ trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit_f_dqs.c 2009-10-16 16:32:57 UTC (rev 4788) @@ -2096,7 +2096,7 @@ static inline void train_ram_on_node(unsigned nodeid, unsigned coreid, struct sys_info *sysinfo, unsigned retcall) { if(coreid) return; // only do it on core0 - struct sys_info *sysinfox = (void*)((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfox = (void*)((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); wait_till_sysinfo_in_ram(); // use pci to get it if(sysinfox->mem_trained[nodeid] == 0x80) { Modified: trunk/coreboot-v2/src/pc80/usbdebug_direct_serial.c =================================================================== --- trunk/coreboot-v2/src/pc80/usbdebug_direct_serial.c 2009-10-16 14:34:50 UTC (rev 4787) +++ trunk/coreboot-v2/src/pc80/usbdebug_direct_serial.c 2009-10-16 16:32:57 UTC (rev 4788) @@ -45,7 +45,7 @@ /* "Find" dbg_info structure in RAM */ dbg_info = (struct ehci_debug_info *) - ((CONFIG_LB_MEM_TOPK << 10) - sizeof(struct ehci_debug_info)); + ((CONFIG_RAMTOP) - sizeof(struct ehci_debug_info)); if (dbg_info->ehci_debug) { dbgp_bulk_write_x(dbg_info, &data, 1); -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
