On Fri, Oct 16, 2009 at 2:28 PM, Hugh Greenberg <[email protected]> wrote:
> I'm getting more output now with r4795:
>
Good. Thanks.
> coreboot-2.3 Fri Oct 16 14:19:51 MDT 2009 starting...
> Enabling routing table for node 00 done.
> Enabling SMP settings
>
(0,1) link=01
> (1,0) link=01
> setup_remote_node: done
> Renaming current temporary node to 01 done.
> Enabling routing table for node 01 done.
> 02 nodes initialized.
> coherent_ht_finalize
> done
> SBLink=00
> NC node|link=00
> entering ht_optimize_link
> pos=0x8a, unfiltered freq_cap=0x8075
> pos=0x8a, filtered freq_cap=0x35
> pos=0xce, unfiltered freq_cap=0x35
> freq_cap1=0x35, freq_cap2=0x15
> dev1 old_freq=0x4, freq=0x4, needs_reset=0x0
> dev2 old_freq=0x4, freq=0x4, needs_reset=0x0
>
This looks like a warm reset. Have you tried it from power on?
I have no idea why it would stop there. The next thing I would do is print
out the routing table when it hangs.
Thanks,
Myles
Index: cbv2/src/northbridge/amd/amdk8/debug.c
===================================================================
--- cbv2.orig/src/northbridge/amd/amdk8/debug.c
+++ cbv2/src/northbridge/amd/amdk8/debug.c
@@ -361,4 +361,54 @@ static void dump_mem(unsigned start, uns
}
print_debug("\r\n");
}
-#endif
+
+static void print_k8regs(void)
+{
+ device_t k8dev=0;
+ u32 val;
+ int i;
+
+ k8dev=PCI_DEV(0,0x18,0);
+ printk_debug("%s: func 0 (%x)\n", __func__, k8dev);
+ val = pci_read_config32(k8dev, 0x40);
+ if (val)
+ printk_debug("0x40 (Routing 0) %x\n", val);
+ val = pci_read_config32(k8dev, 0x44);
+ if (val)
+ printk_debug("0x44 (Routing 1) %x\n", val);
+ val = pci_read_config32(k8dev, 0x60);
+ if (val)
+ printk_debug("0x60 (Node ID) %x\n", val);
+
+ k8dev=PCI_DEV(0,0x18,1);
+ printk_debug("%s: func 1 (%x)\n", __func__, k8dev);
+ val = pci_read_config32(k8dev, 0x40);
+ if (val)
+ printk_debug("0x40 (DRAM Base) %x\n", val);
+ val = pci_read_config32(k8dev, 0x44);
+ if (val)
+ printk_debug("0x44 (DRAM Lim) %x\n", val);
+ val = pci_read_config32(k8dev, 0x48);
+ if (val)
+ printk_debug("0x48 (DRAM Base) %x\n", val);
+ val = pci_read_config32(k8dev, 0x4C);
+ if (val)
+ printk_debug("0x4C (DRAM Lim) %x\n", val);
+ for (i=0x80; i< 0xF0; i+=4) {
+ val = pci_read_config32(k8dev, i);
+ if (val)
+ printk_debug("%x %x\n", i, val);
+ }
+
+ val = pci_read_config32(k8dev, 0xF0);
+ if (val)
+ printk_debug("0xF0 (DRAM Hole) %x\n", val);
+
+ k8dev=PCI_DEV(0,0x18,2);
+ printk_debug("%s: func 2 (%x) nonzero only \n", __func__, k8dev);
+ for (i=0x40; i< 0x84; i+=4) {
+ val = pci_read_config32(k8dev, i);
+ if (val)
+ printk_debug("%x (DRAM Base) %x\n", i, val);
+ }
+}
Index: cbv2/src/cpu/amd/model_fxx/init_cpus.c
===================================================================
--- cbv2.orig/src/cpu/amd/model_fxx/init_cpus.c
+++ cbv2/src/cpu/amd/model_fxx/init_cpus.c
@@ -342,6 +342,7 @@ static unsigned init_cpus(unsigned cpu_i
timeout = wait_cpu_state(bsp_apicid, 0x44);
}
if(timeout) {
+ print_k8regs();
print_initcpu8("while waiting for BSP signal to STOP, timeout in ap ", apicid);
}
lapic_write(LAPIC_MSG_REG, (apicid<<24) | 0x44); // bsp can not check it before stop_this_cpu
--
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