Author: stepan Date: 2009-10-23 21:33:52 +0200 (Fri, 23 Oct 2009) New Revision: 4828
Removed: trunk/coreboot-v2/src/include/pc80/ide.h trunk/coreboot-v2/src/pc80/ide/ trunk/coreboot-v2/src/southbridge/via/vt8231/vt8231.h trunk/coreboot-v2/src/southbridge/via/vt8235/vt8235.h trunk/coreboot-v2/src/southbridge/winbond/ Modified: trunk/coreboot-v2/src/config/Options.lb trunk/coreboot-v2/src/cpu/ppc/ppc4xx/pci_bridge.c trunk/coreboot-v2/src/mainboard/asus/mew-vm/Options.lb trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/Options.lb trunk/coreboot-v2/src/pc80/Config.lb trunk/coreboot-v2/src/southbridge/intel/i82801ca/Config.lb trunk/coreboot-v2/src/southbridge/intel/i82801ca/Makefile.inc trunk/coreboot-v2/src/southbridge/via/vt8231/vt8231.c trunk/coreboot-v2/src/southbridge/via/vt8231/vt8231_acpi.c trunk/coreboot-v2/src/southbridge/via/vt8231/vt8231_ide.c trunk/coreboot-v2/src/southbridge/via/vt8231/vt8231_lpc.c trunk/coreboot-v2/src/southbridge/via/vt8231/vt8231_nic.c trunk/coreboot-v2/src/southbridge/via/vt8235/vt8235.c trunk/coreboot-v2/src/southbridge/via/vt8235/vt8235_ide.c trunk/coreboot-v2/src/southbridge/via/vt8235/vt8235_lpc.c trunk/coreboot-v2/src/southbridge/via/vt8235/vt8235_nic.c trunk/coreboot-v2/src/southbridge/via/vt8235/vt8235_usb.c trunk/coreboot-v2/util/compareboard/compareboard Log: drop a lot of dead code, including an old winbond southbridge from our removed ppc port, some ambiguous use of CONFIG_IDE and an unused ide driver (we dropped the filesystems already to be used with it) (somewhat trivial) Signed-off-by: Stefan Reinauer <[email protected]> Acked-by: Stefan Reinauer <[email protected]> Modified: trunk/coreboot-v2/src/config/Options.lb =================================================================== --- trunk/coreboot-v2/src/config/Options.lb 2009-10-23 18:22:27 UTC (rev 4827) +++ trunk/coreboot-v2/src/config/Options.lb 2009-10-23 19:33:52 UTC (rev 4828) @@ -718,31 +718,6 @@ end ############################################### -# IDE specific options -############################################### - -define CONFIG_IDE - default 0 - export always - comment "Define to include IDE support" -end -define CONFIG_IDE_BOOT_DRIVE - default 0 - export always - comment "Disk number of boot drive" -end -define CONFIG_IDE_SWAB - default none - export used - comment "Swap bytes when reading from IDE device" -end -define CONFIG_IDE_OFFSET - default 0 - export always - comment "Sector at which to start searching for boot image" -end - -############################################### # Options for memory mapped I/O ############################################### Modified: trunk/coreboot-v2/src/cpu/ppc/ppc4xx/pci_bridge.c =================================================================== --- trunk/coreboot-v2/src/cpu/ppc/ppc4xx/pci_bridge.c 2009-10-23 18:22:27 UTC (rev 4827) +++ trunk/coreboot-v2/src/cpu/ppc/ppc4xx/pci_bridge.c 2009-10-23 19:33:52 UTC (rev 4828) @@ -27,7 +27,6 @@ }; struct pci_driver pci_bridge_pci_driver __pci_driver = { - /* w83c553f */ .ops = &pci_bridge_ops, .device = PCI_DEVICE_ID_IBM_405GP, .vendor = PCI_VENDOR_ID_IBM, Deleted: trunk/coreboot-v2/src/include/pc80/ide.h =================================================================== --- trunk/coreboot-v2/src/include/pc80/ide.h 2009-10-23 18:22:27 UTC (rev 4827) +++ trunk/coreboot-v2/src/include/pc80/ide.h 2009-10-23 19:33:52 UTC (rev 4828) @@ -1,211 +0,0 @@ -/* - * UBL, The Universal Talkware Boot Loader - * Copyright (C) 2000 Universal Talkware Inc. - * Copyright (C) 2002 Eric Biederman - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * - */ - -typedef uint64_t sector_t; - -struct controller { - uint16_t cmd_base; - uint16_t ctrl_base; -}; - -struct harddisk_info { - struct controller *ctrl; - uint16_t heads; - uint16_t cylinders; - uint16_t sectors_per_track; - uint8_t model_number[41]; - uint8_t slave; - sector_t sectors; - int address_mode; /* am i lba (0x40) or chs (0x00) */ -#define ADDRESS_MODE_CHS 0 -#define ADDRESS_MODE_LBA 1 -#define ADDRESS_MODE_LBA48 2 -#define ADDRESS_MODE_PACKET 3 - uint32_t hw_sector_size; - unsigned drive_exists : 1; - unsigned slave_absent : 1; - unsigned removable : 1; -}; - - -#define IDE_SECTOR_SIZE 0x200 -#define CDROM_SECTOR_SIZE 0x800 - -#define IDE_BASE0 (0x1F0u) /* primary controller */ -#define IDE_BASE1 (0x170u) /* secondary */ -#define IDE_BASE2 (0x0F0u) /* third */ -#define IDE_BASE3 (0x070u) /* fourth */ - -#define IDE_REG_EXTENDED_OFFSET (0x204u) - -#define IDE_REG_DATA(ctrl) ((ctrl)->cmd_base + 0u) /* word register */ -#define IDE_REG_ERROR(ctrl) ((ctrl)->cmd_base + 1u) -#define IDE_REG_PRECOMP(ctrl) ((ctrl)->cmd_base + 1u) -#define IDE_REG_FEATURE(ctrl) ((ctrl)->cmd_base + 1u) -#define IDE_REG_SECTOR_COUNT(ctrl) ((ctrl)->cmd_base + 2u) -#define IDE_REG_SECTOR_NUMBER(ctrl) ((ctrl)->cmd_base + 3u) -#define IDE_REG_LBA_LOW(ctrl) ((ctrl)->cmd_base + 3u) -#define IDE_REG_CYLINDER_LSB(ctrl) ((ctrl)->cmd_base + 4u) -#define IDE_REG_LBA_MID(ctrl) ((ctrl)->cmd_base + 4u) -#define IDE_REG_CYLINDER_MSB(ctrl) ((ctrl)->cmd_base + 5u) -#define IDE_REG_LBA_HIGH(ctrl) ((ctrl)->cmd_base + 5u) -#define IDE_REG_DRIVEHEAD(ctrl) ((ctrl)->cmd_base + 6u) -#define IDE_REG_DEVICE(ctrl) ((ctrl)->cmd_base + 6u) -#define IDE_REG_STATUS(ctrl) ((ctrl)->cmd_base + 7u) -#define IDE_REG_COMMAND(ctrl) ((ctrl)->cmd_base + 7u) -#define IDE_REG_ALTSTATUS(ctrl) ((ctrl)->ctrl_base + 2u) -#define IDE_REG_DEVICE_CONTROL(ctrl) ((ctrl)->ctrl_base + 2u) - -struct ide_pio_command -{ - uint8_t feature; - uint8_t sector_count; - uint8_t lba_low; - uint8_t lba_mid; - uint8_t lba_high; - uint8_t device; -# define IDE_DH_DEFAULT (0xA0) -# define IDE_DH_HEAD(x) ((x) & 0x0F) -# define IDE_DH_MASTER (0x00) -# define IDE_DH_SLAVE (0x10) -# define IDE_DH_LBA (0x40) -# define IDE_DH_CHS (0x00) - uint8_t command; - uint8_t sector_count2; - uint8_t lba_low2; - uint8_t lba_mid2; - uint8_t lba_high2; -}; - -#define IDE_DEFAULT_COMMAND { 0xFFu, 0x01, 0x00, 0x0000, IDE_DH_DEFAULT } - -#define IDE_ERR_ICRC 0x80 /* ATA Ultra DMA bad CRC */ -#define IDE_ERR_BBK 0x80 /* ATA bad block */ -#define IDE_ERR_UNC 0x40 /* ATA uncorrected error */ -#define IDE_ERR_MC 0x20 /* ATA media change */ -#define IDE_ERR_IDNF 0x10 /* ATA id not found */ -#define IDE_ERR_MCR 0x08 /* ATA media change request */ -#define IDE_ERR_ABRT 0x04 /* ATA command aborted */ -#define IDE_ERR_NTK0 0x02 /* ATA track 0 not found */ -#define IDE_ERR_NDAM 0x01 /* ATA address mark not found */ - -#define IDE_STATUS_BSY 0x80 /* busy */ -#define IDE_STATUS_RDY 0x40 /* ready */ -#define IDE_STATUS_DF 0x20 /* device fault */ -#define IDE_STATUS_WFT 0x20 /* write fault (old name) */ -#define IDE_STATUS_SKC 0x10 /* seek complete */ -#define IDE_STATUS_DRQ 0x08 /* data request */ -#define IDE_STATUS_CORR 0x04 /* corrected */ -#define IDE_STATUS_IDX 0x02 /* index */ -#define IDE_STATUS_ERR 0x01 /* error (ATA) */ -#define IDE_STATUS_CHK 0x01 /* check (ATAPI) */ - -#define IDE_CTRL_HD15 0x08 /* bit should always be set to one */ -#define IDE_CTRL_SRST 0x04 /* soft reset */ -#define IDE_CTRL_NIEN 0x02 /* disable interrupts */ - - -/* Most mandtory and optional ATA commands (from ATA-3), */ - -#define IDE_CMD_CFA_ERASE_SECTORS 0xC0 -#define IDE_CMD_CFA_REQUEST_EXT_ERR_CODE 0x03 -#define IDE_CMD_CFA_TRANSLATE_SECTOR 0x87 -#define IDE_CMD_CFA_WRITE_MULTIPLE_WO_ERASE 0xCD -#define IDE_CMD_CFA_WRITE_SECTORS_WO_ERASE 0x38 -#define IDE_CMD_CHECK_POWER_MODE1 0xE5 -#define IDE_CMD_CHECK_POWER_MODE2 0x98 -#define IDE_CMD_DEVICE_RESET 0x08 -#define IDE_CMD_EXECUTE_DEVICE_DIAGNOSTIC 0x90 -#define IDE_CMD_FLUSH_CACHE 0xE7 -#define IDE_CMD_FORMAT_TRACK 0x50 -#define IDE_CMD_IDENTIFY_DEVICE 0xEC -#define IDE_CMD_IDENTIFY_DEVICE_PACKET 0xA1 -#define IDE_CMD_IDENTIFY_PACKET_DEVICE 0xA1 -#define IDE_CMD_IDLE1 0xE3 -#define IDE_CMD_IDLE2 0x97 -#define IDE_CMD_IDLE_IMMEDIATE1 0xE1 -#define IDE_CMD_IDLE_IMMEDIATE2 0x95 -#define IDE_CMD_INITIALIZE_DRIVE_PARAMETERS 0x91 -#define IDE_CMD_INITIALIZE_DEVICE_PARAMETERS 0x91 -#define IDE_CMD_NOP 0x00 -#define IDE_CMD_PACKET 0xA0 -#define IDE_CMD_READ_BUFFER 0xE4 -#define IDE_CMD_READ_DMA 0xC8 -#define IDE_CMD_READ_DMA_QUEUED 0xC7 -#define IDE_CMD_READ_MULTIPLE 0xC4 -#define IDE_CMD_READ_SECTORS 0x20 -#define IDE_CMD_READ_SECTORS_EXT 0x24 -#define IDE_CMD_READ_VERIFY_SECTORS 0x40 -#define IDE_CMD_RECALIBRATE 0x10 -#define IDE_CMD_SEEK 0x70 -#define IDE_CMD_SET_FEATURES 0xEF -#define IDE_CMD_SET_MAX_ADDR_EXT 0x24 -#define IDE_CMD_SET_MULTIPLE_MODE 0xC6 -#define IDE_CMD_SLEEP1 0xE6 -#define IDE_CMD_SLEEP2 0x99 -#define IDE_CMD_STANDBY1 0xE2 -#define IDE_CMD_STANDBY2 0x96 -#define IDE_CMD_STANDBY_IMMEDIATE1 0xE0 -#define IDE_CMD_STANDBY_IMMEDIATE2 0x94 -#define IDE_CMD_WRITE_BUFFER 0xE8 -#define IDE_CMD_WRITE_DMA 0xCA -#define IDE_CMD_WRITE_DMA_QUEUED 0xCC -#define IDE_CMD_WRITE_MULTIPLE 0xC5 -#define IDE_CMD_WRITE_SECTORS 0x30 -#define IDE_CMD_WRITE_VERIFY 0x3C - -/* IDE_CMD_SET_FEATURE sub commands */ -#define IDE_FEATURE_CFA_ENABLE_8BIT_PIO 0x01 -#define IDE_FEATURE_ENABLE_WRITE_CACHE 0x02 -#define IDE_FEATURE_SET_TRANSFER_MODE 0x03 -#define IDE_FEATURE_ENABLE_POWER_MANAGEMENT 0x05 -#define IDE_FEATURE_ENABLE_POWERUP_IN_STANDBY 0x06 -#define IDE_FEATURE_STANDBY_SPINUP_DRIVE 0x07 -#define IDE_FEATURE_CFA_ENABLE_POWER_MODE1 0x0A -#define IDE_FEATURE_DISABLE_MEDIA_STATUS_NOTIFICATION 0x31 -#define IDE_FEATURE_ENABLE_AUTOMATIC_ACOUSTIC_MANAGEMENT 0x42 -#define IDE_FEATURE_SET_MAXIMUM_HOST_INTERFACE_SECTOR_TIMES 0x43 -#define IDE_FEATURE_DISABLE_READ_LOOKAHEAD 0x55 -#define IDE_FEATURE_ENABLE_RELEASE_INTERRUPT 0x5D -#define IDE_FEATURE_ENABLE_SERVICE_INTERRUPT 0x5E -#define IDE_FEATURE_DISABLE_REVERTING_TO_POWERON_DEFAULTS 0x66 -#define IDE_FEATURE_CFA_DISABLE_8BIT_PIO 0x81 -#define IDE_FEATURE_DISABLE_WRITE_CACHE 0x82 -#define IDE_FEATURE_DISABLE_POWER_MANAGEMENT 0x85 -#define IDE_FEATURE_DISABLE_POWERUP_IN_STANDBY 0x86 -#define IDE_FEATURE_CFA_DISABLE_POWER_MODE1 0x8A -#define IDE_FEATURE_ENABLE_MEDIA_STATUS_NOTIFICATION 0x95 -#define IDE_FEATURE_ENABLE_READ_LOOKAHEAD 0xAA -#define IDE_FEATURE_DISABLE_AUTOMATIC_ACOUSTIC_MANAGEMENT 0xC2 -#define IDE_FEATURE_ENABLE_REVERTING_TO_POWERON_DEFAULTS 0xCC -#define IDE_FEATURE_DISABLE_SERVICE_INTERRUPT 0xDE - -#define IDE_MAX_CONTROLLERS 2 -#define IDE_MAX_DRIVES (IDE_MAX_CONTROLLERS*2) -#define SECTOR_SIZE 512 -#define SECTOR_SHIFT 9 - -/* Maximum block_size that may be set. */ -#define DISK_BUFFER_SIZE (18 * SECTOR_SIZE) - -extern int ide_probe(int drive); -extern int ide_read(int drive, sector_t sector, void *buffer); Modified: trunk/coreboot-v2/src/mainboard/asus/mew-vm/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/mew-vm/Options.lb 2009-10-23 18:22:27 UTC (rev 4827) +++ trunk/coreboot-v2/src/mainboard/asus/mew-vm/Options.lb 2009-10-23 19:33:52 UTC (rev 4828) @@ -38,7 +38,6 @@ uses CONFIG_TTYS0_BASE uses CONFIG_TTYS0_LCS uses CONFIG_UDELAY_TSC -uses CONFIG_IDE ## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. default CONFIG_ROM_SIZE = 512*1024 @@ -73,9 +72,6 @@ ## default CONFIG_HAVE_OPTION_TABLE = 0 -## IDE Support -default CONFIG_IDE = 1 - ### ### coreboot layout values ### Modified: trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/Options.lb 2009-10-23 18:22:27 UTC (rev 4827) +++ trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/Options.lb 2009-10-23 19:33:52 UTC (rev 4828) @@ -44,7 +44,6 @@ uses CONFIG_PCI_ROM_RUN uses CONFIG_DEBUG #uses CONFIG_CPU_OPT -uses CONFIG_IDE ## These are defined in target Config.lb, don't add here uses CONFIG_USE_FALLBACK_IMAGE @@ -228,9 +227,6 @@ ## Select power on after power fail setting default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" -## Things we may not have -default CONFIG_IDE=1 - default CONFIG_DEBUG=1 # default CONFIG_CPU_OPT="-g" Modified: trunk/coreboot-v2/src/pc80/Config.lb =================================================================== --- trunk/coreboot-v2/src/pc80/Config.lb 2009-10-23 18:22:27 UTC (rev 4827) +++ trunk/coreboot-v2/src/pc80/Config.lb 2009-10-23 19:33:52 UTC (rev 4828) @@ -1,4 +1,3 @@ -uses CONFIG_IDE uses CONFIG_UDELAY_IO uses CONFIG_USE_INIT uses CONFIG_ARCH_X86 @@ -12,10 +11,6 @@ object udelay_io.o end -if CONFIG_IDE - dir ide -end - dir vga object keyboard.o Modified: trunk/coreboot-v2/src/southbridge/intel/i82801ca/Config.lb =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82801ca/Config.lb 2009-10-23 18:22:27 UTC (rev 4827) +++ trunk/coreboot-v2/src/southbridge/intel/i82801ca/Config.lb 2009-10-23 19:33:52 UTC (rev 4828) @@ -1,16 +1,8 @@ -uses CONFIG_IDE - config chip.h driver i82801ca.o - driver i82801ca_usb.o - driver i82801ca_lpc.o - -if CONFIG_IDE - driver i82801ca_ide.o -end - +driver i82801ca_ide.o driver i82801ca_ac97.o #driver i82801ca_nic.o driver i82801ca_pci.o Modified: trunk/coreboot-v2/src/southbridge/intel/i82801ca/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82801ca/Makefile.inc 2009-10-23 18:22:27 UTC (rev 4827) +++ trunk/coreboot-v2/src/southbridge/intel/i82801ca/Makefile.inc 2009-10-23 19:33:52 UTC (rev 4828) @@ -1,9 +1,7 @@ driver-y += i82801ca.o driver-y += i82801ca_usb.o driver-y += i82801ca_lpc.o - -driver-$(CONFIG_IDE) += i82801ca_ide.o - +driver-y += i82801ca_ide.o driver-y += i82801ca_ac97.o #driver-y += i82801ca_nic.o driver-y += i82801ca_pci.o Modified: trunk/coreboot-v2/src/southbridge/via/vt8231/vt8231.c =================================================================== --- trunk/coreboot-v2/src/southbridge/via/vt8231/vt8231.c 2009-10-23 18:22:27 UTC (rev 4827) +++ trunk/coreboot-v2/src/southbridge/via/vt8231/vt8231.c 2009-10-23 19:33:52 UTC (rev 4828) @@ -7,7 +7,6 @@ #include <pc80/mc146818rtc.h> #include <pc80/keyboard.h> -#include "vt8231.h" #include "chip.h" /* Base 8231 controller */ Deleted: trunk/coreboot-v2/src/southbridge/via/vt8231/vt8231.h =================================================================== --- trunk/coreboot-v2/src/southbridge/via/vt8231/vt8231.h 2009-10-23 18:22:27 UTC (rev 4827) +++ trunk/coreboot-v2/src/southbridge/via/vt8231/vt8231.h 2009-10-23 19:33:52 UTC (rev 4828) @@ -1,195 +0,0 @@ -/* - * (C) Copyright 2000 - * Rob Taylor, Flying Pig Systems. [email protected]. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - - /* winbond access routines and defines*/ - -/* from the winbond data sheet - - The W83C553F SIO controller with PCI arbiter is a multi-function PCI device. - Function 0 is the ISA bridge, and Function 1 is the bus master IDE controller. -*/ - -/*ISA bridge configuration space*/ - -#define W83C553F_VID 0x10AD -#define W83C553F_DID 0x0565 -#define W83C553F_IDE 0x0105 - -/* Function 0 registers */ -#define W83C553F_PCICONTR 0x40 /*pci control reg*/ -#define W83C553F_SGBAR 0x41 /*scatter/gather base address reg*/ -#define W83C553F_LBCR 0x42 /*Line Buffer Control reg*/ -#define W83C553F_IDEIRCR 0x43 /*IDE Interrupt Routing Control Reg*/ -#define W83C553F_PCIIRCR 0x44 /*PCI Interrupt Routing Control Reg*/ -#define W83C553F_BTBAR 0x46 /*BIOS Timer Base Address Register*/ -#define W83C553F_IPADCR 0x48 /*ISA to PCI Address Decoder Control Register*/ -#define W83C553F_IRADCR 0x49 /*ISA ROM Address Decoder Control Register*/ -#define W83C553F_IPMHSAR 0x4a /*ISA to PCI Memory Hole STart Address Register*/ -#define W83C553F_IPMHSR 0x4b /*ISA to PCI Memory Hols Size Register*/ -#define W83C553F_CDR 0x4c /*Clock Divisor Register*/ -#define W83C553F_CSCR 0x4d /*Chip Select Control Register*/ -#define W83C553F_ATSCR 0x4e /*AT System Control register*/ -#define W83C553F_ATBCR 0x4f /*AT Bus ControL Register*/ -#define W83C553F_IRQBEE0R 0x60 /*IRQ Break Event Enable 0 Register*/ -#define W83C553F_IRQBEE1R 0x61 /*IRQ Break Event Enable 1 Register*/ -#define W83C553F_ABEER 0x62 /*Additional Break Event Enable Register*/ -#define W83C553F_DMABEER 0x63 /*DMA Break Event Enable Register*/ - -/* Function 1 registers */ -#define W83C553F_PIR 0x09 /*Programming Interface Register*/ -#define W83C553F_IDECSR 0x40 /*IDE Control/Status Register*/ - -/* register bit definitions */ -#define W83C553F_IPADCR_MBE512 0x1 -#define W83C553F_IPADCR_MBE640 0x2 -#define W83C553F_IPADCR_IPATOM4 0x10 -#define W83C553F_IPADCR_IPATOM5 0x20 -#define W83C553F_IPADCR_IPATOM6 0x40 -#define W83C553F_IPADCR_IPATOM7 0x80 - -#define W83C553F_CSCR_UBIOSCSE 0x10 -#define W83C553F_CSCR_BIOSWP 0x20 - -#define W83C553F_IDECSR_P0EN 0x01 -#define W83C553F_IDECSR_P0F16 0x02 -#define W83C553F_IDECSR_P1EN 0x10 -#define W83C553F_IDECSR_P1F16 0x20 -#define W83C553F_IDECSR_LEGIRQ 0x800 - -#define W83C553F_ATSCR_ISARE 0x40 -#define W83C553F_ATSCR_FERRE 0x10 -#define W83C553F_ATSCR_P92E 0x04 -#define W83C553F_ATSCR_KRCEE 0x02 -#define W83C553F_ATSCR_KGA20EE 0x01 - -#define W83C553F_PIR_BM 0x80 -#define W83C553F_PIR_P1PROG 0x08 -#define W83C553F_PIR_P1NL 0x04 -#define W83C553F_PIR_P0PROG 0x02 -#define W83C553F_PIR_P0NL 0x01 - -/* - * Interrupt controller - */ -#define W83C553F_PIC1_ICW1 CONFIG_ISA_IO + 0x20 -#define W83C553F_PIC1_ICW2 CONFIG_ISA_IO + 0x21 -#define W83C553F_PIC1_ICW3 CONFIG_ISA_IO + 0x21 -#define W83C553F_PIC1_ICW4 CONFIG_ISA_IO + 0x21 -#define W83C553F_PIC1_OCW1 CONFIG_ISA_IO + 0x21 -#define W83C553F_PIC1_OCW2 CONFIG_ISA_IO + 0x20 -#define W83C553F_PIC1_OCW3 CONFIG_ISA_IO + 0x20 -#define W83C553F_PIC1_ELC CONFIG_ISA_IO + 0x4D0 -#define W83C553F_PIC2_ICW1 CONFIG_ISA_IO + 0xA0 -#define W83C553F_PIC2_ICW2 CONFIG_ISA_IO + 0xA1 -#define W83C553F_PIC2_ICW3 CONFIG_ISA_IO + 0xA1 -#define W83C553F_PIC2_ICW4 CONFIG_ISA_IO + 0xA1 -#define W83C553F_PIC2_OCW1 CONFIG_ISA_IO + 0xA1 -#define W83C553F_PIC2_OCW2 CONFIG_ISA_IO + 0xA0 -#define W83C553F_PIC2_OCW3 CONFIG_ISA_IO + 0xA0 -#define W83C553F_PIC2_ELC CONFIG_ISA_IO + 0x4D1 - -#define W83C553F_TMR1_CMOD CONFIG_ISA_IO + 0x43 - -/* - * DMA controller - */ -#define W83C553F_DMA1 CONFIG_ISA_IO + 0x000 /* channel 0 - 3 */ -#define W83C553F_DMA2 CONFIG_ISA_IO + 0x0C0 /* channel 4 - 7 */ - -/* command/status register bit definitions */ - -#define W83C553F_CS_COM_DACKAL (1<<7) /* DACK# assert level */ -#define W83C553F_CS_COM_DREQSAL (1<<6) /* DREQ sense assert level */ -#define W83C553F_CS_COM_GAP (1<<4) /* group arbitration priority */ -#define W83C553F_CS_COM_CGE (1<<2) /* channel group enable */ - -#define W83C553F_CS_STAT_CH0REQ (1<<4) /* channel 0 (4) DREQ status */ -#define W83C553F_CS_STAT_CH1REQ (1<<5) /* channel 1 (5) DREQ status */ -#define W83C553F_CS_STAT_CH2REQ (1<<6) /* channel 2 (6) DREQ status */ -#define W83C553F_CS_STAT_CH3REQ (1<<7) /* channel 3 (7) DREQ status */ - -#define W83C553F_CS_STAT_CH0TC (1<<0) /* channel 0 (4) TC status */ -#define W83C553F_CS_STAT_CH1TC (1<<1) /* channel 1 (5) TC status */ -#define W83C553F_CS_STAT_CH2TC (1<<2) /* channel 2 (6) TC status */ -#define W83C553F_CS_STAT_CH3TC (1<<3) /* channel 3 (7) TC status */ - -/* mode register bit definitions */ - -#define W83C553F_MODE_TM_DEMAND (0<<6) /* transfer mode - demand */ -#define W83C553F_MODE_TM_SINGLE (1<<6) /* transfer mode - single */ -#define W83C553F_MODE_TM_BLOCK (2<<6) /* transfer mode - block */ -#define W83C553F_MODE_TM_CASCADE (3<<6) /* transfer mode - cascade */ -#define W83C553F_MODE_ADDRDEC (1<<5) /* address increment/decrement select */ -#define W83C553F_MODE_AUTOINIT (1<<4) /* autoinitialize enable */ -#define W83C553F_MODE_TT_VERIFY (0<<2) /* transfer type - verify */ -#define W83C553F_MODE_TT_WRITE (1<<2) /* transfer type - write */ -#define W83C553F_MODE_TT_READ (2<<2) /* transfer type - read */ -#define W83C553F_MODE_TT_ILLEGAL (3<<2) /* transfer type - illegal */ -#define W83C553F_MODE_CH0SEL (0<<0) /* channel 0 (4) select */ -#define W83C553F_MODE_CH1SEL (1<<0) /* channel 1 (5) select */ -#define W83C553F_MODE_CH2SEL (2<<0) /* channel 2 (6) select */ -#define W83C553F_MODE_CH3SEL (3<<0) /* channel 3 (7) select */ - -/* request register bit definitions */ - -#define W83C553F_REQ_CHSERREQ (1<<2) /* channel service request */ -#define W83C553F_REQ_CH0SEL (0<<0) /* channel 0 (4) select */ -#define W83C553F_REQ_CH1SEL (1<<0) /* channel 1 (5) select */ -#define W83C553F_REQ_CH2SEL (2<<0) /* channel 2 (6) select */ -#define W83C553F_REQ_CH3SEL (3<<0) /* channel 3 (7) select */ - -/* write single mask bit register bit definitions */ - -#define W83C553F_WSMB_CHMASKSEL (1<<2) /* channel mask select */ -#define W83C553F_WSMB_CH0SEL (0<<0) /* channel 0 (4) select */ -#define W83C553F_WSMB_CH1SEL (1<<0) /* channel 1 (5) select */ -#define W83C553F_WSMB_CH2SEL (2<<0) /* channel 2 (6) select */ -#define W83C553F_WSMB_CH3SEL (3<<0) /* channel 3 (7) select */ - -/* read/write all mask bits register bit definitions */ - -#define W83C553F_RWAMB_CH0MASK (1<<0) /* channel 0 (4) mask */ -#define W83C553F_RWAMB_CH1MASK (1<<1) /* channel 1 (5) mask */ -#define W83C553F_RWAMB_CH2MASK (1<<2) /* channel 2 (6) mask */ -#define W83C553F_RWAMB_CH3MASK (1<<3) /* channel 3 (7) mask */ - -/* typedefs */ - -#define W83C553F_DMA1_CS 0x8 -#define W83C553F_DMA1_WR 0x9 -#define W83C553F_DMA1_WSMB 0xA -#define W83C553F_DMA1_WM 0xB -#define W83C553F_DMA1_CBP 0xC -#define W83C553F_DMA1_MC 0xD -#define W83C553F_DMA1_CM 0xE -#define W83C553F_DMA1_RWAMB 0xF - -#define W83C553F_DMA2_CS 0xD0 -#define W83C553F_DMA2_WR 0xD2 -#define W83C553F_DMA2_WSMB 0xD4 -#define W83C553F_DMA2_WM 0xD6 -#define W83C553F_DMA2_CBP 0xD8 -#define W83C553F_DMA2_MC 0xDA -#define W83C553F_DMA2_CM 0xDC -#define W83C553F_DMA2_RWAMB 0xDE - -void initialise_w83c553f(void); Modified: trunk/coreboot-v2/src/southbridge/via/vt8231/vt8231_acpi.c =================================================================== --- trunk/coreboot-v2/src/southbridge/via/vt8231/vt8231_acpi.c 2009-10-23 18:22:27 UTC (rev 4827) +++ trunk/coreboot-v2/src/southbridge/via/vt8231/vt8231_acpi.c 2009-10-23 19:33:52 UTC (rev 4828) @@ -3,7 +3,6 @@ #include <device/pci.h> #include <device/pci_ops.h> #include <device/pci_ids.h> -#include "vt8231.h" static void acpi_init(struct device *dev) { Modified: trunk/coreboot-v2/src/southbridge/via/vt8231/vt8231_ide.c =================================================================== --- trunk/coreboot-v2/src/southbridge/via/vt8231/vt8231_ide.c 2009-10-23 18:22:27 UTC (rev 4827) +++ trunk/coreboot-v2/src/southbridge/via/vt8231/vt8231_ide.c 2009-10-23 19:33:52 UTC (rev 4828) @@ -3,7 +3,6 @@ #include <device/pci.h> #include <device/pci_ops.h> #include <device/pci_ids.h> -#include "vt8231.h" #include "chip.h" static void ide_init(struct device *dev) Modified: trunk/coreboot-v2/src/southbridge/via/vt8231/vt8231_lpc.c =================================================================== --- trunk/coreboot-v2/src/southbridge/via/vt8231/vt8231_lpc.c 2009-10-23 18:22:27 UTC (rev 4827) +++ trunk/coreboot-v2/src/southbridge/via/vt8231/vt8231_lpc.c 2009-10-23 19:33:52 UTC (rev 4828) @@ -6,7 +6,6 @@ #include <pc80/mc146818rtc.h> -#include "vt8231.h" #include "chip.h" /* PIRQ init Modified: trunk/coreboot-v2/src/southbridge/via/vt8231/vt8231_nic.c =================================================================== --- trunk/coreboot-v2/src/southbridge/via/vt8231/vt8231_nic.c 2009-10-23 18:22:27 UTC (rev 4827) +++ trunk/coreboot-v2/src/southbridge/via/vt8231/vt8231_nic.c 2009-10-23 19:33:52 UTC (rev 4828) @@ -3,7 +3,6 @@ #include <device/pci.h> #include <device/pci_ops.h> #include <device/pci_ids.h> -#include "vt8231.h" /* * Enable the ethernet device and turn off stepping (because it is integrated Modified: trunk/coreboot-v2/src/southbridge/via/vt8235/vt8235.c =================================================================== --- trunk/coreboot-v2/src/southbridge/via/vt8235/vt8235.c 2009-10-23 18:22:27 UTC (rev 4827) +++ trunk/coreboot-v2/src/southbridge/via/vt8235/vt8235.c 2009-10-23 19:33:52 UTC (rev 4828) @@ -5,7 +5,6 @@ #include <device/pci_ids.h> #include <pc80/keyboard.h> #include <pc80/i8259.h> -#include "vt8235.h" #include "chip.h" /* Deleted: trunk/coreboot-v2/src/southbridge/via/vt8235/vt8235.h =================================================================== --- trunk/coreboot-v2/src/southbridge/via/vt8235/vt8235.h 2009-10-23 18:22:27 UTC (rev 4827) +++ trunk/coreboot-v2/src/southbridge/via/vt8235/vt8235.h 2009-10-23 19:33:52 UTC (rev 4828) @@ -1,195 +0,0 @@ -/* - * (C) Copyright 2000 - * Rob Taylor, Flying Pig Systems. [email protected]. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - - /* winbond access routines and defines*/ - -/* from the winbond data sheet - - The W83C553F SIO controller with PCI arbiter is a multi-function PCI device. - Function 0 is the ISA bridge, and Function 1 is the bus master IDE controller. -*/ - -/*ISA bridge configuration space*/ - -#define W83C553F_VID 0x10AD -#define W83C553F_DID 0x0565 -#define W83C553F_IDE 0x0105 - -/* Function 0 registers */ -#define W83C553F_PCICONTR 0x40 /*pci control reg*/ -#define W83C553F_SGBAR 0x41 /*scatter/gather base address reg*/ -#define W83C553F_LBCR 0x42 /*Line Buffer Control reg*/ -#define W83C553F_IDEIRCR 0x43 /*IDE Interrupt Routing Control Reg*/ -#define W83C553F_PCIIRCR 0x44 /*PCI Interrupt Routing Control Reg*/ -#define W83C553F_BTBAR 0x46 /*BIOS Timer Base Address Register*/ -#define W83C553F_IPADCR 0x48 /*ISA to PCI Address Decoder Control Register*/ -#define W83C553F_IRADCR 0x49 /*ISA ROM Address Decoder Control Register*/ -#define W83C553F_IPMHSAR 0x4a /*ISA to PCI Memory Hole STart Address Register*/ -#define W83C553F_IPMHSR 0x4b /*ISA to PCI Memory Hols Size Register*/ -#define W83C553F_CDR 0x4c /*Clock Divisor Register*/ -#define W83C553F_CSCR 0x4d /*Chip Select Control Register*/ -#define W83C553F_ATSCR 0x4e /*AT System Control register*/ -#define W83C553F_ATBCR 0x4f /*AT Bus ControL Register*/ -#define W83C553F_IRQBEE0R 0x60 /*IRQ Break Event Enable 0 Register*/ -#define W83C553F_IRQBEE1R 0x61 /*IRQ Break Event Enable 1 Register*/ -#define W83C553F_ABEER 0x62 /*Additional Break Event Enable Register*/ -#define W83C553F_DMABEER 0x63 /*DMA Break Event Enable Register*/ - -/* Function 1 registers */ -#define W83C553F_PIR 0x09 /*Programming Interface Register*/ -#define W83C553F_IDECSR 0x40 /*IDE Control/Status Register*/ - -/* register bit definitions */ -#define W83C553F_IPADCR_MBE512 0x1 -#define W83C553F_IPADCR_MBE640 0x2 -#define W83C553F_IPADCR_IPATOM4 0x10 -#define W83C553F_IPADCR_IPATOM5 0x20 -#define W83C553F_IPADCR_IPATOM6 0x40 -#define W83C553F_IPADCR_IPATOM7 0x80 - -#define W83C553F_CSCR_UBIOSCSE 0x10 -#define W83C553F_CSCR_BIOSWP 0x20 - -#define W83C553F_IDECSR_P0EN 0x01 -#define W83C553F_IDECSR_P0F16 0x02 -#define W83C553F_IDECSR_P1EN 0x10 -#define W83C553F_IDECSR_P1F16 0x20 -#define W83C553F_IDECSR_LEGIRQ 0x800 - -#define W83C553F_ATSCR_ISARE 0x40 -#define W83C553F_ATSCR_FERRE 0x10 -#define W83C553F_ATSCR_P92E 0x04 -#define W83C553F_ATSCR_KRCEE 0x02 -#define W83C553F_ATSCR_KGA20EE 0x01 - -#define W83C553F_PIR_BM 0x80 -#define W83C553F_PIR_P1PROG 0x08 -#define W83C553F_PIR_P1NL 0x04 -#define W83C553F_PIR_P0PROG 0x02 -#define W83C553F_PIR_P0NL 0x01 - -/* - * Interrupt controller - */ -#define W83C553F_PIC1_ICW1 CONFIG_ISA_IO + 0x20 -#define W83C553F_PIC1_ICW2 CONFIG_ISA_IO + 0x21 -#define W83C553F_PIC1_ICW3 CONFIG_ISA_IO + 0x21 -#define W83C553F_PIC1_ICW4 CONFIG_ISA_IO + 0x21 -#define W83C553F_PIC1_OCW1 CONFIG_ISA_IO + 0x21 -#define W83C553F_PIC1_OCW2 CONFIG_ISA_IO + 0x20 -#define W83C553F_PIC1_OCW3 CONFIG_ISA_IO + 0x20 -#define W83C553F_PIC1_ELC CONFIG_ISA_IO + 0x4D0 -#define W83C553F_PIC2_ICW1 CONFIG_ISA_IO + 0xA0 -#define W83C553F_PIC2_ICW2 CONFIG_ISA_IO + 0xA1 -#define W83C553F_PIC2_ICW3 CONFIG_ISA_IO + 0xA1 -#define W83C553F_PIC2_ICW4 CONFIG_ISA_IO + 0xA1 -#define W83C553F_PIC2_OCW1 CONFIG_ISA_IO + 0xA1 -#define W83C553F_PIC2_OCW2 CONFIG_ISA_IO + 0xA0 -#define W83C553F_PIC2_OCW3 CONFIG_ISA_IO + 0xA0 -#define W83C553F_PIC2_ELC CONFIG_ISA_IO + 0x4D1 - -#define W83C553F_TMR1_CMOD CONFIG_ISA_IO + 0x43 - -/* - * DMA controller - */ -#define W83C553F_DMA1 CONFIG_ISA_IO + 0x000 /* channel 0 - 3 */ -#define W83C553F_DMA2 CONFIG_ISA_IO + 0x0C0 /* channel 4 - 7 */ - -/* command/status register bit definitions */ - -#define W83C553F_CS_COM_DACKAL (1<<7) /* DACK# assert level */ -#define W83C553F_CS_COM_DREQSAL (1<<6) /* DREQ sense assert level */ -#define W83C553F_CS_COM_GAP (1<<4) /* group arbitration priority */ -#define W83C553F_CS_COM_CGE (1<<2) /* channel group enable */ - -#define W83C553F_CS_STAT_CH0REQ (1<<4) /* channel 0 (4) DREQ status */ -#define W83C553F_CS_STAT_CH1REQ (1<<5) /* channel 1 (5) DREQ status */ -#define W83C553F_CS_STAT_CH2REQ (1<<6) /* channel 2 (6) DREQ status */ -#define W83C553F_CS_STAT_CH3REQ (1<<7) /* channel 3 (7) DREQ status */ - -#define W83C553F_CS_STAT_CH0TC (1<<0) /* channel 0 (4) TC status */ -#define W83C553F_CS_STAT_CH1TC (1<<1) /* channel 1 (5) TC status */ -#define W83C553F_CS_STAT_CH2TC (1<<2) /* channel 2 (6) TC status */ -#define W83C553F_CS_STAT_CH3TC (1<<3) /* channel 3 (7) TC status */ - -/* mode register bit definitions */ - -#define W83C553F_MODE_TM_DEMAND (0<<6) /* transfer mode - demand */ -#define W83C553F_MODE_TM_SINGLE (1<<6) /* transfer mode - single */ -#define W83C553F_MODE_TM_BLOCK (2<<6) /* transfer mode - block */ -#define W83C553F_MODE_TM_CASCADE (3<<6) /* transfer mode - cascade */ -#define W83C553F_MODE_ADDRDEC (1<<5) /* address increment/decrement select */ -#define W83C553F_MODE_AUTOINIT (1<<4) /* autoinitialize enable */ -#define W83C553F_MODE_TT_VERIFY (0<<2) /* transfer type - verify */ -#define W83C553F_MODE_TT_WRITE (1<<2) /* transfer type - write */ -#define W83C553F_MODE_TT_READ (2<<2) /* transfer type - read */ -#define W83C553F_MODE_TT_ILLEGAL (3<<2) /* transfer type - illegal */ -#define W83C553F_MODE_CH0SEL (0<<0) /* channel 0 (4) select */ -#define W83C553F_MODE_CH1SEL (1<<0) /* channel 1 (5) select */ -#define W83C553F_MODE_CH2SEL (2<<0) /* channel 2 (6) select */ -#define W83C553F_MODE_CH3SEL (3<<0) /* channel 3 (7) select */ - -/* request register bit definitions */ - -#define W83C553F_REQ_CHSERREQ (1<<2) /* channel service request */ -#define W83C553F_REQ_CH0SEL (0<<0) /* channel 0 (4) select */ -#define W83C553F_REQ_CH1SEL (1<<0) /* channel 1 (5) select */ -#define W83C553F_REQ_CH2SEL (2<<0) /* channel 2 (6) select */ -#define W83C553F_REQ_CH3SEL (3<<0) /* channel 3 (7) select */ - -/* write single mask bit register bit definitions */ - -#define W83C553F_WSMB_CHMASKSEL (1<<2) /* channel mask select */ -#define W83C553F_WSMB_CH0SEL (0<<0) /* channel 0 (4) select */ -#define W83C553F_WSMB_CH1SEL (1<<0) /* channel 1 (5) select */ -#define W83C553F_WSMB_CH2SEL (2<<0) /* channel 2 (6) select */ -#define W83C553F_WSMB_CH3SEL (3<<0) /* channel 3 (7) select */ - -/* read/write all mask bits register bit definitions */ - -#define W83C553F_RWAMB_CH0MASK (1<<0) /* channel 0 (4) mask */ -#define W83C553F_RWAMB_CH1MASK (1<<1) /* channel 1 (5) mask */ -#define W83C553F_RWAMB_CH2MASK (1<<2) /* channel 2 (6) mask */ -#define W83C553F_RWAMB_CH3MASK (1<<3) /* channel 3 (7) mask */ - -/* typedefs */ - -#define W83C553F_DMA1_CS 0x8 -#define W83C553F_DMA1_WR 0x9 -#define W83C553F_DMA1_WSMB 0xA -#define W83C553F_DMA1_WM 0xB -#define W83C553F_DMA1_CBP 0xC -#define W83C553F_DMA1_MC 0xD -#define W83C553F_DMA1_CM 0xE -#define W83C553F_DMA1_RWAMB 0xF - -#define W83C553F_DMA2_CS 0xD0 -#define W83C553F_DMA2_WR 0xD2 -#define W83C553F_DMA2_WSMB 0xD4 -#define W83C553F_DMA2_WM 0xD6 -#define W83C553F_DMA2_CBP 0xD8 -#define W83C553F_DMA2_MC 0xDA -#define W83C553F_DMA2_CM 0xDC -#define W83C553F_DMA2_RWAMB 0xDE - -void initialise_w83c553f(void); Modified: trunk/coreboot-v2/src/southbridge/via/vt8235/vt8235_ide.c =================================================================== --- trunk/coreboot-v2/src/southbridge/via/vt8235/vt8235_ide.c 2009-10-23 18:22:27 UTC (rev 4827) +++ trunk/coreboot-v2/src/southbridge/via/vt8235/vt8235_ide.c 2009-10-23 19:33:52 UTC (rev 4828) @@ -3,7 +3,6 @@ #include <device/pci_ops.h> #include <device/pci_ids.h> #include <console/console.h> -#include "vt8235.h" #include "chip.h" static void ide_init(struct device *dev) Modified: trunk/coreboot-v2/src/southbridge/via/vt8235/vt8235_lpc.c =================================================================== --- trunk/coreboot-v2/src/southbridge/via/vt8235/vt8235_lpc.c 2009-10-23 18:22:27 UTC (rev 4827) +++ trunk/coreboot-v2/src/southbridge/via/vt8235/vt8235_lpc.c 2009-10-23 19:33:52 UTC (rev 4828) @@ -7,7 +7,6 @@ #include <pc80/mc146818rtc.h> -#include "vt8235.h" #include "chip.h" /* The epia-m is really short on interrupts available, so PCI interupts A & D are ganged togther and so are B & C. Modified: trunk/coreboot-v2/src/southbridge/via/vt8235/vt8235_nic.c =================================================================== --- trunk/coreboot-v2/src/southbridge/via/vt8235/vt8235_nic.c 2009-10-23 18:22:27 UTC (rev 4827) +++ trunk/coreboot-v2/src/southbridge/via/vt8235/vt8235_nic.c 2009-10-23 19:33:52 UTC (rev 4828) @@ -3,7 +3,6 @@ #include <device/pci.h> #include <device/pci_ops.h> #include <device/pci_ids.h> -#include "vt8235.h" /* * Enable the ethernet device and turn off stepping (because it is integrated Modified: trunk/coreboot-v2/src/southbridge/via/vt8235/vt8235_usb.c =================================================================== --- trunk/coreboot-v2/src/southbridge/via/vt8235/vt8235_usb.c 2009-10-23 18:22:27 UTC (rev 4827) +++ trunk/coreboot-v2/src/southbridge/via/vt8235/vt8235_usb.c 2009-10-23 19:33:52 UTC (rev 4828) @@ -3,7 +3,6 @@ #include <device/pci.h> #include <device/pci_ops.h> #include <device/pci_ids.h> -#include "vt8235.h" /* really nothing to do here, both usb 1.1 & 2.0 are normal PCI devices and so get resources allocated properly. They are part of the southbridge and are enabled in the chip enable function for the southbridge */ @@ -43,4 +42,4 @@ .vendor = PCI_VENDOR_ID_VIA, .device = PCI_DEVICE_ID_VIA_82C586_2, }; -*/ \ No newline at end of file +*/ Modified: trunk/coreboot-v2/util/compareboard/compareboard =================================================================== --- trunk/coreboot-v2/util/compareboard/compareboard 2009-10-23 18:22:27 UTC (rev 4827) +++ trunk/coreboot-v2/util/compareboard/compareboard 2009-10-23 19:33:52 UTC (rev 4828) @@ -43,8 +43,6 @@ -e "/^CONFIG_ROMBASE / d" \ -e "/^CONFIG_ROM_IMAGE_SIZE / d" \ -e "/^CONFIG_STACK_SIZE / d" \ - -e "/^CONFIG_IDE_BOOT_DRIVE / d" \ - -e "/^CONFIG_IDE_OFFSET / d" \ -e "/^CONFIG_GDB_STUB / d" \ $A/old > $A/old.filtered sed \ -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
