Author: myles Date: 2009-10-24 00:53:26 +0200 (Sat, 24 Oct 2009) New Revision: 4830
Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/cache_as_ram_auto.c trunk/coreboot-v2/src/mainboard/broadcom/blast/cache_as_ram_auto.c trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/cache_as_ram_auto.c trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c trunk/coreboot-v2/src/mainboard/hp/dl145_g3/cache_as_ram_auto.c trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/cache_as_ram_auto.c trunk/coreboot-v2/src/mainboard/iwill/dk8s2/cache_as_ram_auto.c trunk/coreboot-v2/src/mainboard/iwill/dk8x/cache_as_ram_auto.c trunk/coreboot-v2/src/mainboard/msi/ms7260/cache_as_ram_auto.c trunk/coreboot-v2/src/mainboard/msi/ms9185/cache_as_ram_auto.c trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/cache_as_ram_auto.c trunk/coreboot-v2/src/mainboard/sunw/ultra40/cache_as_ram_auto.c trunk/coreboot-v2/src/mainboard/supermicro/h8dme/cache_as_ram_auto.c trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/cache_as_ram_auto.c trunk/coreboot-v2/src/mainboard/tyan/s2895/cache_as_ram_auto.c trunk/coreboot-v2/src/mainboard/tyan/s2912/cache_as_ram_auto.c trunk/coreboot-v2/src/northbridge/amd/amdk8/incoherent_ht.c Log: Drop dead K8_SCAN_PCI_BUS code. It's a bad idea to scan the PCI busses before RAM is initialized, and no one does it. Trivial. Signed-off-by: Myles Watson <[email protected]> Acked-by: Myles Watson <[email protected]> Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/cache_as_ram_auto.c 2009-10-23 21:57:42 UTC (rev 4829) +++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/cache_as_ram_auto.c 2009-10-23 22:53:26 UTC (rev 4830) @@ -10,10 +10,8 @@ #define QRANK_DIMM_SUPPORT 1 //used by incoherent_ht -//#define K8_SCAN_PCI_BUS 1 //#define K8_ALLOCATE_IO_RANGE 1 - //used by init_cpus and fidvid #define K8_SET_FIDVID 0 //if we want to wait for core1 done before DQS training, set it to 0 Modified: trunk/coreboot-v2/src/mainboard/broadcom/blast/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/broadcom/blast/cache_as_ram_auto.c 2009-10-23 21:57:42 UTC (rev 4829) +++ trunk/coreboot-v2/src/mainboard/broadcom/blast/cache_as_ram_auto.c 2009-10-23 22:53:26 UTC (rev 4830) @@ -1,9 +1,6 @@ #define ASSEMBLY 1 #define __ROMCC__ - -//#define K8_SCAN_PCI_BUS 1 - #define QRANK_DIMM_SUPPORT 1 #if CONFIG_LOGICAL_CPUS==1 Modified: trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/cache_as_ram_auto.c 2009-10-23 21:57:42 UTC (rev 4829) +++ trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/cache_as_ram_auto.c 2009-10-23 22:53:26 UTC (rev 4830) @@ -27,9 +27,7 @@ #define RAMINIT_SYSINFO 1 #define K8_ALLOCATE_IO_RANGE 1 -//#define K8_SCAN_PCI_BUS 1 - #define QRANK_DIMM_SUPPORT 1 #if CONFIG_LOGICAL_CPUS==1 Modified: trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c 2009-10-23 21:57:42 UTC (rev 4829) +++ trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c 2009-10-23 22:53:26 UTC (rev 4830) @@ -25,9 +25,7 @@ #define RAMINIT_SYSINFO 1 #define K8_ALLOCATE_IO_RANGE 1 -//#define K8_SCAN_PCI_BUS 1 - #define QRANK_DIMM_SUPPORT 1 #if CONFIG_LOGICAL_CPUS==1 Modified: trunk/coreboot-v2/src/mainboard/hp/dl145_g3/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/hp/dl145_g3/cache_as_ram_auto.c 2009-10-23 21:57:42 UTC (rev 4829) +++ trunk/coreboot-v2/src/mainboard/hp/dl145_g3/cache_as_ram_auto.c 2009-10-23 22:53:26 UTC (rev 4830) @@ -31,7 +31,6 @@ #define RAMINIT_SYSINFO 1 #define K8_ALLOCATE_IO_RANGE 1 -//#define K8_SCAN_PCI_BUS 1 #define QRANK_DIMM_SUPPORT 1 Modified: trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/cache_as_ram_auto.c 2009-10-23 21:57:42 UTC (rev 4829) +++ trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/cache_as_ram_auto.c 2009-10-23 22:53:26 UTC (rev 4830) @@ -10,10 +10,8 @@ #define QRANK_DIMM_SUPPORT 1 //used by incoherent_ht -//#define K8_SCAN_PCI_BUS 1 //#define K8_ALLOCATE_IO_RANGE 1 - //used by init_cpus and fidvid #define K8_SET_FIDVID 0 //if we want to wait for core1 done before DQS training, set it to 0 Modified: trunk/coreboot-v2/src/mainboard/iwill/dk8s2/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/iwill/dk8s2/cache_as_ram_auto.c 2009-10-23 21:57:42 UTC (rev 4829) +++ trunk/coreboot-v2/src/mainboard/iwill/dk8s2/cache_as_ram_auto.c 2009-10-23 22:53:26 UTC (rev 4830) @@ -10,10 +10,8 @@ #define QRANK_DIMM_SUPPORT 1 //used by incoherent_ht -//#define K8_SCAN_PCI_BUS 1 //#define K8_ALLOCATE_IO_RANGE 1 - //used by init_cpus and fidvid #define K8_SET_FIDVID 0 //if we want to wait for core1 done before DQS training, set it to 0 Modified: trunk/coreboot-v2/src/mainboard/iwill/dk8x/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/iwill/dk8x/cache_as_ram_auto.c 2009-10-23 21:57:42 UTC (rev 4829) +++ trunk/coreboot-v2/src/mainboard/iwill/dk8x/cache_as_ram_auto.c 2009-10-23 22:53:26 UTC (rev 4830) @@ -10,10 +10,8 @@ #define QRANK_DIMM_SUPPORT 1 //used by incoherent_ht -//#define K8_SCAN_PCI_BUS 1 //#define K8_ALLOCATE_IO_RANGE 1 - //used by init_cpus and fidvid #define K8_SET_FIDVID 0 //if we want to wait for core1 done before DQS training, set it to 0 Modified: trunk/coreboot-v2/src/mainboard/msi/ms7260/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms7260/cache_as_ram_auto.c 2009-10-23 21:57:42 UTC (rev 4829) +++ trunk/coreboot-v2/src/mainboard/msi/ms7260/cache_as_ram_auto.c 2009-10-23 22:53:26 UTC (rev 4830) @@ -31,7 +31,6 @@ #define RAMINIT_SYSINFO 1 #define K8_ALLOCATE_IO_RANGE 1 -// #define K8_SCAN_PCI_BUS 1 /* ? */ #define QRANK_DIMM_SUPPORT 1 #if CONFIG_LOGICAL_CPUS == 1 #define SET_NB_CFG_54 1 Modified: trunk/coreboot-v2/src/mainboard/msi/ms9185/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms9185/cache_as_ram_auto.c 2009-10-23 21:57:42 UTC (rev 4829) +++ trunk/coreboot-v2/src/mainboard/msi/ms9185/cache_as_ram_auto.c 2009-10-23 22:53:26 UTC (rev 4830) @@ -35,10 +35,8 @@ #define QRANK_DIMM_SUPPORT 1 //used by incoherent_ht -//#define K8_SCAN_PCI_BUS 1 //#define K8_ALLOCATE_IO_RANGE 1 - //used by init_cpus and fidvid #define K8_SET_FIDVID 1 //if we want to wait for core1 done before DQS training, set it to 0 Modified: trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/cache_as_ram_auto.c 2009-10-23 21:57:42 UTC (rev 4829) +++ trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/cache_as_ram_auto.c 2009-10-23 22:53:26 UTC (rev 4830) @@ -25,9 +25,7 @@ #define RAMINIT_SYSINFO 1 #define K8_ALLOCATE_IO_RANGE 1 -//#define K8_SCAN_PCI_BUS 1 - #define QRANK_DIMM_SUPPORT 1 #if CONFIG_LOGICAL_CPUS==1 Modified: trunk/coreboot-v2/src/mainboard/sunw/ultra40/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/sunw/ultra40/cache_as_ram_auto.c 2009-10-23 21:57:42 UTC (rev 4829) +++ trunk/coreboot-v2/src/mainboard/sunw/ultra40/cache_as_ram_auto.c 2009-10-23 22:53:26 UTC (rev 4830) @@ -3,9 +3,7 @@ #define K8_ALLOCATE_IO_RANGE 1 -//#define K8_SCAN_PCI_BUS 1 - #define QRANK_DIMM_SUPPORT 1 #if CONFIG_LOGICAL_CPUS==1 Modified: trunk/coreboot-v2/src/mainboard/supermicro/h8dme/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/h8dme/cache_as_ram_auto.c 2009-10-23 21:57:42 UTC (rev 4829) +++ trunk/coreboot-v2/src/mainboard/supermicro/h8dme/cache_as_ram_auto.c 2009-10-23 22:53:26 UTC (rev 4830) @@ -22,7 +22,6 @@ #define RAMINIT_SYSINFO 1 #define K8_ALLOCATE_IO_RANGE 1 -// #define K8_SCAN_PCI_BUS 1 #define QRANK_DIMM_SUPPORT 1 Modified: trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/cache_as_ram_auto.c 2009-10-23 21:57:42 UTC (rev 4829) +++ trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/cache_as_ram_auto.c 2009-10-23 22:53:26 UTC (rev 4830) @@ -25,9 +25,7 @@ #define RAMINIT_SYSINFO 1 #define K8_ALLOCATE_IO_RANGE 1 -//#define K8_SCAN_PCI_BUS 1 - #define QRANK_DIMM_SUPPORT 1 #if CONFIG_LOGICAL_CPUS==1 Modified: trunk/coreboot-v2/src/mainboard/tyan/s2895/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2895/cache_as_ram_auto.c 2009-10-23 21:57:42 UTC (rev 4829) +++ trunk/coreboot-v2/src/mainboard/tyan/s2895/cache_as_ram_auto.c 2009-10-23 22:53:26 UTC (rev 4830) @@ -2,7 +2,6 @@ #define __ROMCC__ #define K8_ALLOCATE_IO_RANGE 1 -//#define K8_SCAN_PCI_BUS 1 #define QRANK_DIMM_SUPPORT 1 Modified: trunk/coreboot-v2/src/mainboard/tyan/s2912/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2912/cache_as_ram_auto.c 2009-10-23 21:57:42 UTC (rev 4829) +++ trunk/coreboot-v2/src/mainboard/tyan/s2912/cache_as_ram_auto.c 2009-10-23 22:53:26 UTC (rev 4830) @@ -25,9 +25,7 @@ #define RAMINIT_SYSINFO 1 #define K8_ALLOCATE_IO_RANGE 1 -//#define K8_SCAN_PCI_BUS 1 - #define QRANK_DIMM_SUPPORT 1 #if CONFIG_LOGICAL_CPUS==1 Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/incoherent_ht.c =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdk8/incoherent_ht.c 2009-10-23 21:57:42 UTC (rev 4829) +++ trunk/coreboot-v2/src/northbridge/amd/amdk8/incoherent_ht.c 2009-10-23 22:53:26 UTC (rev 4830) @@ -15,10 +15,6 @@ #define RAMINIT_SYSINFO 0 #endif -#ifndef K8_SCAN_PCI_BUS - #define K8_SCAN_PCI_BUS 0 -#endif - #ifndef K8_ALLOCATE_IO_RANGE #define K8_ALLOCATE_IO_RANGE 0 #endif @@ -299,123 +295,7 @@ return needs_reset; } -#if (CONFIG_USE_DCACHE_RAM == 1) && (K8_SCAN_PCI_BUS == 1) - #if RAMINIT_SYSINFO == 1 -static void ht_setup_chainx(device_t udev, uint8_t upos, uint8_t bus, unsigned offset_unitid, struct sys_info *sysinfo); -static int scan_pci_bus( unsigned bus , struct sys_info *sysinfo) -#else -static int ht_setup_chainx(device_t udev, uint8_t upos, uint8_t bus, unsigned offset_unitid); -static int scan_pci_bus( unsigned bus) -#endif -{ - /* - here we already can access PCI_DEV(bus, 0, 0) to PCI_DEV(bus, 0x1f, 0x7) - So We can scan these devices to find out if they are bridge - If it is pci bridge, We need to set busn in bridge, and go on - For ht bridge, We need to set the busn in bridge and ht_setup_chainx, and the scan_pci_bus - */ - unsigned int devfn; - unsigned new_bus; - unsigned max_bus; - - new_bus = (bus & 0xff); // mask out the reset_needed - - if(new_bus<0x40) { - max_bus = 0x3f; - } else if (new_bus<0x80) { - max_bus = 0x7f; - } else if (new_bus<0xc0) { - max_bus = 0xbf; - } else { - max_bus = 0xff; - } - - new_bus = bus; - - for (devfn = 0; devfn <= 0xff; devfn++) { - uint8_t hdr_type; - uint16_t class; - uint32_t buses; - device_t dev; - uint16_t cr; - dev = PCI_DEV((bus & 0xff), ((devfn>>3) & 0x1f), (devfn & 0x7)); - hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE); - class = pci_read_config16(dev, PCI_CLASS_DEVICE); - - switch(hdr_type & 0x7f) { /* header type */ - case PCI_HEADER_TYPE_BRIDGE: - if (class != PCI_CLASS_BRIDGE_PCI) goto bad; - /* set the bus range dev */ - - /* Clear all status bits and turn off memory, I/O and master enables. */ - cr = pci_read_config16(dev, PCI_COMMAND); - pci_write_config16(dev, PCI_COMMAND, 0x0000); - pci_write_config16(dev, PCI_STATUS, 0xffff); - - buses = pci_read_config32(dev, PCI_PRIMARY_BUS); - - buses &= 0xff000000; - new_bus++; - buses |= (((unsigned int) (bus & 0xff) << 0) | - ((unsigned int) (new_bus & 0xff) << 8) | - ((unsigned int) max_bus << 16)); - pci_write_config32(dev, PCI_PRIMARY_BUS, buses); - - /* here we need to figure out if dev is a ht bridge - if it is ht bridge, we need to call ht_setup_chainx at first - Not verified --- yhlu - */ - uint8_t upos; - upos = ht_lookup_host_capability(dev); // one func one ht sub - if (upos) { // sub ht chain - uint8_t busn; - busn = (new_bus & 0xff); - /* Make certain the HT bus is not enumerated */ - ht_collapse_previous_enumeration(busn, 0); - /* scan the ht chain */ - #if RAMINIT_SYSINFO == 1 - ht_setup_chainx(dev,upos,busn, 0, sysinfo); // don't need offset unitid - #else - new_bus |= (ht_setup_chainx(dev, upos, busn, 0)<<16); // store reset_needed to upword - #endif - } - - #if RAMINIT_SYSINFO == 1 - new_bus = scan_pci_bus(new_bus, sysinfo); - #else - new_bus = scan_pci_bus(new_bus); - #endif - /* set real max bus num in that */ - - buses = (buses & 0xff00ffff) | - ((unsigned int) (new_bus & 0xff) << 16); - pci_write_config32(dev, PCI_PRIMARY_BUS, buses); - - pci_write_config16(dev, PCI_COMMAND, cr); - - break; - default: - bad: - ; - } - - /* if this is not a multi function device, - * or the device is not present don't waste - * time probing another function. - * Skip to next device. - */ - if ( ((devfn & 0x07) == 0x00) && ((hdr_type & 0x80) != 0x80)) - { - devfn += 0x07; - } - } - - return new_bus; -} -#endif - -#if RAMINIT_SYSINFO == 1 static void ht_setup_chainx(device_t udev, uint8_t upos, uint8_t bus, unsigned offset_unitid, struct sys_info *sysinfo) #else static int ht_setup_chainx(device_t udev, uint8_t upos, uint8_t bus, unsigned offset_unitid) @@ -777,9 +657,6 @@ unsigned regpos; uint32_t dword; uint8_t busn; - #if (CONFIG_USE_DCACHE_RAM == 1) && (K8_SCAN_PCI_BUS == 1) - unsigned bus; - #endif unsigned offset_unitid = 0; reg = pci_read_config32(PCI_DEV(0,0x18,1), 0xe0 + i * 4); @@ -814,15 +691,6 @@ reset_needed |= ht_setup_chainx(udev,upos,busn, offset_unitid); //all not #endif - #if (CONFIG_USE_DCACHE_RAM == 1) && (K8_SCAN_PCI_BUS == 1) - /* You can use use this in romcc, because there is function call in romcc, recursive will kill you */ - bus = busn; // we need 32 bit -#if RAMINIT_SYSINFO == 1 - scan_pci_bus(bus, sysinfo); -#else - reset_needed |= (scan_pci_bus(bus)>>16); // take out reset_needed that stored in upword -#endif - #endif } #if RAMINIT_SYSINFO == 0 -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
