On Tue, Dec 22, 2009 at 04:11:06PM -0700, Myles Watson wrote:
> This is broken, but I'm not sure if it's the dump or the register value. It
> shouldn't affect the IO, though. That register looked fine. It seems like
> IO is broken for you not to be able to start the other processors or
> complete the mcp55 init.
>
> You could print out PCI_DEV(0,0x18,0) @ 0x6C to make sure that the lower
> bits are what you expect. The ones I'd look at are the default link (bits
> 11,3,2), disable routing bit (bit 0).
>
> The default link should be 2. The disable routing bit can tell you if it's
> important that the routing registers are messed up.
Hrm. If I'm reading that right with this code
u32 xxx = pci_read_config32(PCI_DEV(0, 0x18, 0), 0x6c);
printk_debug("0x%04x\n",xxx);
then what comes out does not look very good:
0xf870
which is
1111100001110000
So the default link is 0, and the Routing Table Disable bit is set to zero.
You mentioned bit 11 - that seems to be marked as 'reserved' in the BKDG for
fam10?
Thanks,
Ward.
--
Ward Vandewege <w...@fsf.org>
Free Software Foundation - Senior Systems Administrator
--
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
