> -----Original Message----- > From: Knut Kujat [mailto:[email protected]] > Sent: Wednesday, December 30, 2009 3:09 AM > To: Myles Watson > Cc: [email protected] > Subject: Re: [coreboot] Problems porting H8dmr_fam10 to H8qme-2+ > > Myles Watson escribió: > >>> Unfortunately, it's undocumented, so you have a couple of options: > >>> 1. Look at http://www.coreboot.org/Nvidia_MCP55_Porting_Notes > >>> 2. Decode the ACPI interrrupt assignments > >>> > >>> Either way you may need to look at the interrupt assignments in Linux > >>> when booted with the factory BIOS. > >>> > >> I'm wondering if it isn't possible to just read those registers out > once > >> booted with a factory BIOS? > >> > > You can. You still have to make the mptable and irq table match, which > > requires you to know what the values mean. > > > > > at irq table you mean this values: > > write_pirq_info(pirq_info, m->bus_mcp55[0], ((sbdn+6)<<3)|0, 0x1, > 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); <<< this > > pirq_info++; slot_num++; > > for(i=1; i< sysconf.hc_possible_num; i++) { > if(!(sysconf.pci1234[i] & 0x1) ) continue; > unsigned busn = (sysconf.pci1234[i] >> 12) & 0xff; > unsigned devn = sysconf.hcdn[i] & 0xff; > > write_pirq_info(pirq_info, busn, (devn<<3)|0, 0x1, 0xdef8, 0x2, > 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); <<< and this. > pirq_info++; slot_num++; > } Yes. I've never actually used it because I used the ACPI DSDT to specify the same things, but that's what I meant.
> Sorry for those noob questions but this is getting much deeper i thought > it would go. ;) No problem. > OK I'll will first try to make my irqs work after. Because I think most > of the trouble is coming from there. Sure. > One difference I noticed between my lspci -tvnn output and coreboot is > that the ati es 1000 is at bus 6 on the lspci output and on bus 7 at > coreboot. > > +-05.0 nVidia Corporation MCP55 SATA Controller [10de:037f] > +-05.1 nVidia Corporation MCP55 SATA Controller [10de:037f] > +-05.2 nVidia Corporation MCP55 SATA Controller [10de:037f] > +-06.0-[01]----01.0 ATI Technologies Inc ES1000 [1002:515e] > +-0a.0-[02]-- > +-0b.0-[03]-- > +-0c.0-[04]-- The way I read this is device 6.0 has bus number 1 with device 1. > and > > PCI: 00:07.0 resource base 0 size 0 align 20 gran 20 limit ffffffff > flags 80202 index 20 > PCI: 01:01.0 links 0 child on link 0 NULL > PCI: 01:01.0 resource base 0 size 8000000 align 27 gran 27 limit > ffffffff flags 1200 index 10 > PCI: 01:01.0 resource base 0 size 100 align 8 gran 8 limit ffff > flags 100 index 14 > PCI: 01:01.0 resource base 0 size 10000 align 16 gran 16 limit > ffffffff flags 200 index 18 > PCI: 01:01.0 resource base 0 size 20000 align 17 gran 17 limit > ffffffff flags 2200 index 30 > > Is this just a different kind of enumeration or an error? Just a different kind of enumeration. HyperTransport devices can be enumerated at different offsets (in HT terminology "assigned a different UnitID") with no problem. Good luck. Myles -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
