> > My understanding was that CAR refers to L2. As long as nothing gets > > replaced from the L2, everything is as it should be. ROM contents can > > always be fetched again, so that's not critical for correctness. > > This is OK, but L2 CAR is in more detail described in fam11h otherwise AMD > always just speaks about L1 CAR. the fam11h needs some extra tweaks to > various > MSR to disables speculative fills if I remember correctly. This is the > reason > why I see this a bit dangerous, perhaps older CPUs needs this too. > > I think we should mark the XIP region as WP instead of WB (check the > fam11h BKDG). I wish I knew more about it. I haven't done much with fam10h or anything with fam11h.
> Anyway - I tried with UC copy looks like it is not so slow... > > I have in works the patch for the register clobber cleanup plus I will do > some > patch for saving the coreboot mem to resume area... but perhaps on Sunday. > Tomorrow bit of skiing, but if you are curious, here is the patch. It just > fixes > the clobber stuff for the assembly routines, it has bitten me already > while > dumping the MSRs... the ECX value contained some garbage, and rdmsr did > some > exception. Good catch! Myles -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
