Hello, This patch reads SPD data and sets the DRB registers so it no longer hard code for 64MB in bank 0. Theoretically I can stick three 256MB sticks and it'll read 768MB.
I referred to both the SPD spec and 440BX datasheet when I wrote this, but it's too late at night in Toronto so testing will have to wait :-). As such this is for the highly adventurous to see and I don't expect this to be committed just yet. Also a question related to this: How can I get romcc to provide me an assembly listing of a C file compiled? I want to see the assembly code that compiling this generates. Anyway, I got tired of trying to trace the vendor BIOS I have and just coded this up from spec from scratch, so this should legally be safe, and thus... Signed-off-by: Keith Hui <[email protected]>
440bxraminit.patch
Description: Binary data
-- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
