Author: uwe Date: Mon Mar 1 21:16:38 2010 New Revision: 5184 URL: http://tracker.coreboot.org/trac/coreboot/changeset/5184
Log: Whitespace changes to make s2912_fam10/ms9652_fam10 more similar. Also, fix another typo in the ms9652 board name. Signed-off-by: Uwe Hermann <[email protected]> Acked-by: Uwe Hermann <[email protected]> Modified: trunk/src/mainboard/msi/ms9652_fam10/Kconfig trunk/src/mainboard/msi/ms9652_fam10/resourcemap.c trunk/src/mainboard/msi/ms9652_fam10/romstage.c trunk/src/mainboard/msi/ms9652_fam10/spd_addr.h trunk/src/mainboard/tyan/s2912_fam10/Kconfig trunk/src/mainboard/tyan/s2912_fam10/get_bus_conf.c trunk/src/mainboard/tyan/s2912_fam10/mptable.c trunk/src/mainboard/tyan/s2912_fam10/romstage.c Modified: trunk/src/mainboard/msi/ms9652_fam10/Kconfig ============================================================================== --- trunk/src/mainboard/msi/ms9652_fam10/Kconfig Mon Mar 1 18:21:15 2010 (r5183) +++ trunk/src/mainboard/msi/ms9652_fam10/Kconfig Mon Mar 1 21:16:38 2010 (r5184) @@ -134,7 +134,7 @@ config MAINBOARD_PART_NUMBER string - default "MS-9252" + default "MS-9652" depends on BOARD_MSI_MS9652_FAM10 config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID Modified: trunk/src/mainboard/msi/ms9652_fam10/resourcemap.c ============================================================================== --- trunk/src/mainboard/msi/ms9652_fam10/resourcemap.c Mon Mar 1 18:21:15 2010 (r5183) +++ trunk/src/mainboard/msi/ms9652_fam10/resourcemap.c Mon Mar 1 21:16:38 2010 (r5184) @@ -161,7 +161,7 @@ * 1 = base/limit registers i are read-only * [ 7: 4] Reserved * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address + * This field defines the upper address bits of a 40bit address * that defines the start of memory-mapped I/O region i */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000, @@ -218,7 +218,7 @@ * [ 3: 2] Reserved * [ 4: 4] VGA Enable * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the + * 1 = matches all address < 64K and where A[9:0] is in the * range 3B0-3BB or 3C0-3DF independen of the base & limit registers * [ 5: 5] ISA Enable * 0 = ISA matches Disabled @@ -226,7 +226,7 @@ * from matching agains this base/limit pair * [11: 6] Reserved * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n + * This field defines the start of PCI I/O region n * [31:25] Reserved */ /* Verified against board configuration registers after normal proprietary BIOS boot */ Modified: trunk/src/mainboard/msi/ms9652_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms9652_fam10/romstage.c Mon Mar 1 18:21:15 2010 (r5183) +++ trunk/src/mainboard/msi/ms9652_fam10/romstage.c Mon Mar 1 21:16:38 2010 (r5184) @@ -50,9 +50,9 @@ #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" - static void post_code(u8 value) { - outb(value, 0x80); - } +static void post_code(u8 value) { + outb(value, 0x80); +} #if CONFIG_USE_FAILOVER_IMAGE==0 #include "arch/i386/lib/console.c" @@ -153,20 +153,17 @@ static void sio_setup(void) { - - unsigned value; - uint32_t dword; - uint8_t byte; - - byte = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b); - byte |= 0x20; - pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte); - - dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0); - dword |= (1<<0); - pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword); - - + unsigned value; + uint32_t dword; + uint8_t byte; + + byte = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b); + byte |= 0x20; + pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte); + + dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0); + dword |= (1<<0); + pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword); } void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) @@ -281,10 +278,10 @@ #endif val = cpuid_eax(1); - printk_debug("BSP Family_Model: %08x \n", val); + printk_debug("BSP Family_Model: %08x\n", val); printk_debug("*sysinfo range: ["); print_debug_hex32((u32)sysinfo); print_debug(","); print_debug_hex32((u32)sysinfo+sizeof(struct sys_info)); print_debug("]\n"); - printk_debug("bsp_apicid = %02x \n", bsp_apicid); - printk_debug("cpu_init_detectedx = %08x \n", cpu_init_detectedx); + printk_debug("bsp_apicid = %02x\n", bsp_apicid); + printk_debug("cpu_init_detectedx = %08x\n", cpu_init_detectedx); /* Setup sysinfo defaults */ set_sysinfo_in_ram(0); @@ -300,12 +297,12 @@ /* Setup nodes PCI space and start core 0 AP init. */ finalize_node_setup(sysinfo); - printk_debug("finalize_node_setup done \n"); + printk_debug("finalize_node_setup done\n"); /* Setup any mainboard PCI settings etc. */ - printk_debug("setup_mb_resource_map begin \n"); + printk_debug("setup_mb_resource_map begin\n"); setup_mb_resource_map(); - printk_debug("setup_mb_resource_map end \n"); + printk_debug("setup_mb_resource_map end\n"); post_code(0x36); /* wait for all the APs core0 started by finalize_node_setup. */ @@ -329,7 +326,7 @@ #if FAM10_SET_FIDVID == 1 msr = rdmsr(0xc0010071); - printk_debug("\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); + printk_debug("\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); /* FIXME: The sb fid change may survive the warm reset and only * need to be done once.*/ @@ -347,7 +344,7 @@ /* show final fid and vid */ msr=rdmsr(0xc0010071); - printk_debug("End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); + printk_debug("End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); #endif wants_reset = mcp55_early_setup_x(); Modified: trunk/src/mainboard/msi/ms9652_fam10/spd_addr.h ============================================================================== --- trunk/src/mainboard/msi/ms9652_fam10/spd_addr.h Mon Mar 1 18:21:15 2010 (r5183) +++ trunk/src/mainboard/msi/ms9652_fam10/spd_addr.h Mon Mar 1 21:16:38 2010 (r5184) @@ -19,7 +19,7 @@ /** * This file defines the SPD addresses for the mainboard. Must be included in - * cache_as_ram_auto.c + * romstage.c */ #define RC00 0 Modified: trunk/src/mainboard/tyan/s2912_fam10/Kconfig ============================================================================== --- trunk/src/mainboard/tyan/s2912_fam10/Kconfig Mon Mar 1 18:21:15 2010 (r5183) +++ trunk/src/mainboard/tyan/s2912_fam10/Kconfig Mon Mar 1 21:16:38 2010 (r5184) @@ -27,7 +27,7 @@ hex default 0xc4000 depends on BOARD_TYAN_S2912_FAM10 - + config DCACHE_RAM_SIZE hex default 0x0c000 @@ -39,7 +39,7 @@ depends on BOARD_TYAN_S2912_FAM10 config APIC_ID_OFFSET - hex + hex default 0 depends on BOARD_TYAN_S2912_FAM10 @@ -65,7 +65,7 @@ config LB_CKS_LOC int - default 123 + default 123 depends on BOARD_TYAN_S2912_FAM10 config MAINBOARD_PART_NUMBER @@ -75,7 +75,7 @@ config PCI_64BIT_PREF_MEM bool - default n + default n depends on BOARD_TYAN_S2912_FAM10 config HAVE_FALLBACK_BOOT @@ -104,7 +104,7 @@ depends on BOARD_TYAN_S2912_FAM10 config HW_MEM_HOLE_SIZE_AUTO_INC - bool + bool default n depends on BOARD_TYAN_S2912_FAM10 @@ -114,7 +114,7 @@ depends on BOARD_TYAN_S2912_FAM10 config HT_CHAIN_END_UNITID_BASE - hex + hex default 0x20 depends on BOARD_TYAN_S2912_FAM10 @@ -124,12 +124,12 @@ depends on BOARD_TYAN_S2912_FAM10 config SERIAL_CPU_INIT - bool + bool default n depends on BOARD_TYAN_S2912_FAM10 config WAIT_BEFORE_CPUS_INIT - bool + bool default n depends on BOARD_TYAN_S2912_FAM10 Modified: trunk/src/mainboard/tyan/s2912_fam10/get_bus_conf.c ============================================================================== --- trunk/src/mainboard/tyan/s2912_fam10/get_bus_conf.c Mon Mar 1 18:21:15 2010 (r5183) +++ trunk/src/mainboard/tyan/s2912_fam10/get_bus_conf.c Mon Mar 1 21:16:38 2010 (r5184) @@ -68,7 +68,6 @@ void get_bus_conf(void) { - unsigned apicid_base; struct mb_sysconf_t *m; @@ -134,5 +133,4 @@ apicid_base = CONFIG_MAX_PHYSICAL_CPUS; #endif m->apicid_mcp55 = apicid_base+0; - } Modified: trunk/src/mainboard/tyan/s2912_fam10/mptable.c ============================================================================== --- trunk/src/mainboard/tyan/s2912_fam10/mptable.c Mon Mar 1 18:21:15 2010 (r5183) +++ trunk/src/mainboard/tyan/s2912_fam10/mptable.c Mon Mar 1 21:16:38 2010 (r5184) @@ -100,7 +100,7 @@ } - /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, m->apicid_mcp55, 0x0); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x1, m->apicid_mcp55, 0x1); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, m->apicid_mcp55, 0x2); Modified: trunk/src/mainboard/tyan/s2912_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2912_fam10/romstage.c Mon Mar 1 18:21:15 2010 (r5183) +++ trunk/src/mainboard/tyan/s2912_fam10/romstage.c Mon Mar 1 21:16:38 2010 (r5184) @@ -150,10 +150,8 @@ #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c" #include "northbridge/amd/amdfam10/early_ht.c" - static void sio_setup(void) { - unsigned value; uint32_t dword; uint8_t byte; @@ -278,10 +276,10 @@ #endif val = cpuid_eax(1); - printk_debug("BSP Family_Model: %08x \n", val); + printk_debug("BSP Family_Model: %08x\n", val); printk_debug("*sysinfo range: ["); print_debug_hex32((u32)sysinfo); print_debug(","); print_debug_hex32((u32)sysinfo+sizeof(struct sys_info)); print_debug("]\n"); - printk_debug("bsp_apicid = %02x \n", bsp_apicid); - printk_debug("cpu_init_detectedx = %08x \n", cpu_init_detectedx); + printk_debug("bsp_apicid = %02x\n", bsp_apicid); + printk_debug("cpu_init_detectedx = %08x\n", cpu_init_detectedx); /* Setup sysinfo defaults */ set_sysinfo_in_ram(0); @@ -322,7 +320,7 @@ #if FAM10_SET_FIDVID == 1 msr = rdmsr(0xc0010071); - printk_debug("\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); + printk_debug("\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); /* FIXME: The sb fid change may survive the warm reset and only * need to be done once.*/ @@ -340,7 +338,7 @@ /* show final fid and vid */ msr=rdmsr(0xc0010071); - printk_debug("End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); + printk_debug("End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); #endif wants_reset = mcp55_early_setup_x(); -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
