Author: uwe Date: Fri Mar 5 17:31:41 2010 New Revision: 5188 URL: http://tracker.coreboot.org/trac/coreboot/changeset/5188
Log: Add support for the ASUS P2B-LS mainboard. Signed-off-by: Keith Hui <[email protected]> Acked-by: Uwe Hermann <[email protected]> Added: trunk/src/mainboard/asus/p2b-ls/ trunk/src/mainboard/asus/p2b-ls/Kconfig trunk/src/mainboard/asus/p2b-ls/chip.h trunk/src/mainboard/asus/p2b-ls/devicetree.cb trunk/src/mainboard/asus/p2b-ls/irq_tables.c trunk/src/mainboard/asus/p2b-ls/mainboard.c trunk/src/mainboard/asus/p2b-ls/romstage.c Modified: trunk/src/mainboard/asus/Kconfig Modified: trunk/src/mainboard/asus/Kconfig ============================================================================== --- trunk/src/mainboard/asus/Kconfig Fri Mar 5 17:18:38 2010 (r5187) +++ trunk/src/mainboard/asus/Kconfig Fri Mar 5 17:31:41 2010 (r5188) @@ -27,6 +27,7 @@ source "src/mainboard/asus/p2b/Kconfig" source "src/mainboard/asus/p2b-d/Kconfig" source "src/mainboard/asus/p2b-ds/Kconfig" +source "src/mainboard/asus/p2b-ls/Kconfig" source "src/mainboard/asus/p2b-f/Kconfig" source "src/mainboard/asus/p3b-f/Kconfig" source "src/mainboard/asus/m2v-mx_se/Kconfig" Added: trunk/src/mainboard/asus/p2b-ls/Kconfig ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/asus/p2b-ls/Kconfig Fri Mar 5 17:31:41 2010 (r5188) @@ -0,0 +1,52 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2010 Keith Hui <[email protected]> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +config BOARD_ASUS_P2B_LS + bool "P2B-LS" + select ARCH_X86 + select CPU_INTEL_SLOT_1 + select NORTHBRIDGE_INTEL_I440BX + select SOUTHBRIDGE_INTEL_I82371EB + select SUPERIO_WINBOND_W83977TF + select ROMCC + select HAVE_PIRQ_TABLE + select UDELAY_TSC + select BOARD_ROMSIZE_KB_256 + +config MAINBOARD_DIR + string + default asus/p2b-ls + depends on BOARD_ASUS_P2B_LS + +config MAINBOARD_PART_NUMBER + string + default "P2B-LS" + depends on BOARD_ASUS_P2B_LS + +config HAVE_OPTION_TABLE + bool + default n + depends on BOARD_ASUS_P2B_LS + +config IRQ_SLOT_COUNT + int + default 8 + depends on BOARD_ASUS_P2B_LS + Added: trunk/src/mainboard/asus/p2b-ls/chip.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/asus/p2b-ls/chip.h Fri Mar 5 17:31:41 2010 (r5188) @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Uwe Hermann <[email protected]> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; +struct mainboard_config {}; Added: trunk/src/mainboard/asus/p2b-ls/devicetree.cb ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/asus/p2b-ls/devicetree.cb Fri Mar 5 17:31:41 2010 (r5188) @@ -0,0 +1,59 @@ +chip northbridge/intel/i440bx # Northbridge + device apic_cluster 0 on # APIC cluster + chip cpu/intel/slot_1 # CPU + device apic 0 on end # APIC + end + end + device pci_domain 0 on # PCI domain + device pci 0.0 on end # Host bridge + device pci 1.0 on end # PCI/AGP bridge + chip southbridge/intel/i82371eb # Southbridge + device pci 4.0 on # ISA bridge + chip superio/winbond/w83977tf # Super I/O (FIXME: It's W83977EF!) + device pnp 3f0.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 3f0.1 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 3f0.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 3f0.3 on # COM2 / IR + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 3f0.5 on # PS/2 keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 # PS/2 keyboard interrupt + irq 0x72 = 12 # PS/2 mouse interrupt + end + device pnp 3f0.7 on # GPIO 1 + end + device pnp 3f0.8 on # GPIO 2 + end + device pnp 3f0.a on # ACPI + end + end + end + device pci 4.1 on end # IDE + device pci 4.2 on end # USB + device pci 4.3 on end # ACPI + device pci 6.0 on end # Onboard SCSI + device pci 7.0 on end # Onboard LAN + register "ide0_enable" = "1" + register "ide1_enable" = "1" + register "ide_legacy_enable" = "1" + # Enable UDMA/33 for higher speed if your IDE device(s) support it. + register "ide0_drive0_udma33_enable" = "0" + register "ide0_drive1_udma33_enable" = "0" + register "ide1_drive0_udma33_enable" = "0" + register "ide1_drive1_udma33_enable" = "0" + end + end +end Added: trunk/src/mainboard/asus/p2b-ls/irq_tables.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/asus/p2b-ls/irq_tables.c Fri Mar 5 17:31:41 2010 (r5188) @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Keith Hui <[email protected]> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/pirq_routing.h> + +const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, + PIRQ_VERSION, + 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ + 0x00, /* Interrupt router bus */ + (0x04 << 3) | 0x0, /* Interrupt router device */ + 0, /* IRQs devoted exclusively to PCI usage */ + 0x8086, /* Vendor */ + 0x122e, /* Device */ + 0, /* Miniport */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ + 0x10, /* Checksum (has to be set to some value that + * would give 0 after the sum of all bytes + * for this structure (including checksum). + */ + { + /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + {0x00, (0x0c << 3) | 0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}}, 0x1, 0x0}, + {0x00, (0x0b << 3) | 0x0, {{0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}}, 0x2, 0x0}, + {0x00, (0x0a << 3) | 0x0, {{0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}}, 0x3, 0x0}, + {0x00, (0x09 << 3) | 0x0, {{0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}}, 0x4, 0x0}, + {0x00, (0x04 << 3) | 0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}}, 0x0, 0x0}, + {0x00, (0x01 << 3) | 0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}}, 0x0, 0x0}, + {0x00, (0x06 << 3) | 0x0, {{0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}}, 0x0, 0x0}, + {0x00, (0x07 << 3) | 0x0, {{0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}}, 0x0, 0x0}, + } +}; + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + return copy_pirq_routing_table(addr); +} Added: trunk/src/mainboard/asus/p2b-ls/mainboard.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/asus/p2b-ls/mainboard.c Fri Mar 5 17:31:41 2010 (r5188) @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Uwe Hermann <[email protected]> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/device.h> +#include "chip.h" + +struct chip_operations mainboard_ops = { + CHIP_NAME("ASUS P2B-LS Mainboard") +}; Added: trunk/src/mainboard/asus/p2b-ls/romstage.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/asus/p2b-ls/romstage.c Fri Mar 5 17:31:41 2010 (r5188) @@ -0,0 +1,75 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Uwe Hermann <[email protected]> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define ASSEMBLY 1 +#define __PRE_RAM__ + +#include <stdint.h> +#include <device/pci_def.h> +#include <arch/io.h> +#include <device/pnp_def.h> +#include <arch/romcc_io.h> +#include <arch/hlt.h> +#include <stdlib.h> +#include "pc80/serial.c" +#include "arch/i386/lib/console.c" +#include "lib/ramtest.c" +#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" +#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" +#include "northbridge/intel/i440bx/raminit.h" +#include "lib/debug.c" +#include "pc80/udelay_io.c" +#include "lib/delay.c" +#include "cpu/x86/mtrr/earlymtrr.c" +#include "cpu/x86/bist.h" +/* FIXME: The ASUS P2B-LS has a Winbond W83977EF, actually. */ +#include "superio/winbond/w83977tf/w83977tf_early_serial.c" + +#define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1) + +static inline int spd_read_byte(unsigned int device, unsigned int address) +{ + return smbus_read_byte(device, address); +} + +#include "northbridge/intel/i440bx/raminit.c" +#include "northbridge/intel/i440bx/debug.c" + +static void main(unsigned long bist) +{ + if (bist == 0) + early_mtrr_init(); + + /* FIXME: The ASUS P2B-LS has a Winbond W83977EF, actually. */ + w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + uart_init(); + console_init(); + report_bist_failure(bist); + + /* Enable access to the full ROM chip, needed very early by CBFS. */ + i82371eb_enable_rom(PCI_DEV(0, 4, 0)); /* ISA bridge at 00:04.0. */ + + enable_smbus(); + /* dump_spd_registers(); */ + sdram_set_registers(); + sdram_set_spd_registers(); + sdram_enable(); + /* ram_check(0, 640 * 1024); */ +} -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
