/* * This file is part of the coreboot project. * * Copyright (C) 2007-2008 Uwe Hermann * Copyright (C) 2010 Keith Hui * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include #include #include #include #include "i440bx.h" #include "raminit.h" /*----------------------------------------------------------------------------- Macros and definitions. -----------------------------------------------------------------------------*/ /* Debugging macros. */ #if CONFIG_DEBUG_RAM_SETUP #define PRINT_DEBUG(x) print_debug(x) #define PRINT_DEBUG_HEX8(x) print_debug_hex8(x) #define PRINT_DEBUG_HEX16(x) print_debug_hex16(x) #define PRINT_DEBUG_HEX32(x) print_debug_hex32(x) #define DUMPNORTH() dump_pci_device(PCI_DEV(0, 0, 0)) #else #define PRINT_DEBUG(x) #define PRINT_DEBUG_HEX8(x) #define PRINT_DEBUG_HEX16(x) #define PRINT_DEBUG_HEX32(x) #define DUMPNORTH() #endif /* PCI_DEV(0, 0, 0), pre-calculated */ #define NB 0 /* SDRAMC[7:5] - SDRAM Mode Select (SMS). */ #define RAM_COMMAND_NORMAL 0x0 #define RAM_COMMAND_NOP 0x1 #define RAM_COMMAND_PRECHARGE 0x2 #define RAM_COMMAND_MRS 0x3 #define RAM_COMMAND_CBR 0x4 /* Map the JEDEC SPD refresh rates (array index) to 440BX refresh rates as * defined in DRAMC[2:0]. * * [0] == Normal 15.625 us -> 15.6 us * [1] == Reduced(.25X) 3.9 us -> 7.8 ns * [2] == Reduced(.5X) 7.8 us -> 7.8 us * [3] == Extended(2x) 31.3 us -> 31.2 us * [4] == Extended(4x) 62.5 us -> 62.4 us * [5] == Extended(8x) 125 us -> 124.8 us */ static const uint32_t refresh_rate_map[] = { 1, 5, 5, 2, 3, 4 }; /* Table format: register, bitmask, value. */ static const long register_values[] = { /* NBXCFG - NBX Configuration Register * 0x50 - 0x53 * * [31:24] SDRAM Row Without ECC * 0 = ECC components are populated in this row * 1 = ECC components are not populated in this row * [23:19] Reserved * [18:18] Host Bus Fast Data Ready Enable (HBFDRE) * Assertion of DRAM data on host bus occurs... * 0 = ...one clock after sampling snoop results (default) * 1 = ...on the same clock the snoop result is being sampled * (this mode is faster by one clock cycle) * [17:17] ECC - EDO static Drive mode * 0 = Normal mode (default) * 1 = ECC signals are always driven * [16:16] IDSEL_REDIRECT * 0 = IDSEL1 is allocated to this bridge (default) * 1 = IDSEL7 is allocated to this bridge * [15:15] WSC# Handshake Disable * 1 = Uni-processor mode * 0 = Dual-processor mode with external IOAPIC (default) * [14:14] Intel Reserved * [13:12] Host/DRAM Frequency (Bit 13 is externally strapped) * 00 = 100 MHz * 01 = Reserved * 10 = 66 MHz * 11 = Reserved * [11:11] AGP to PCI Access Enable * 1 = Enable * 0 = Disable * [10:10] PCI Agent to Aperture Access Disable * 1 = Disable * 0 = Enable (default) * [09:09] Aperture Access Global Enable * 1 = Enable * 0 = Disable * [08:07] DRAM Data Integrity Mode (DDIM) * 00 = Non-ECC * 01 = EC-only * 10 = ECC Mode * 11 = ECC Mode with hardware scrubbing enabled * [06:06] ECC Diagnostic Mode Enable (EDME) * 1 = Enable * 0 = Normal operation mode (default) * [05:05] MDA Present (MDAP) * Works in conjunction with the VGA_EN bit. * VGA_EN MDAP * 0 x All VGA cycles are sent to PCI * 1 0 All VGA cycles are sent to AGP * 1 1 All VGA cycles are sent to AGP, except for * cycles in the MDA range. * [04:04] Reserved * [03:03] USWC Write Post During I/O Bridge Access Enable (UWPIO) * 1 = Enable * 0 = Disable * [02:02] In-Order Queue Depth (IOQD) * 1 = In-order queue = maximum * 0 = A7# is sampled asserted (i.e., 0) * [01:00] Reserved */ NBXCFG + 0, 0x00, 0x0c, // TODO: Bit 15 should be 0 for multiprocessor boards NBXCFG + 1, 0xf0, 0x8a, NBXCFG + 2, 0x00, 0x04, /* DRAMC - DRAM Control Register * 0x57 * * [7:6] Reserved * [5:5] Module Mode Configuration (MMCONFIG) * This bit is set by an external strapping option. The * combination of this bit and the SDRAMPWR bit (SDRAMC register) * determine the functioning of the CKE signals. * 1 = 3 DIMM, CKE0 only, self-refresh entry not staggered. SDRAM * dynamic power down unavailable. * Note: With MMCONFIG strapped to 1, AGP must be disabled. * [4:3] DRAM Type (DT) * 00 = EDO * 01 = SDRAM * 10 = Registered SDRAM * 11 = Reserved * Note: EDO, SDRAM and Registered SDRAM cannot be mixed. * [2:0] DRAM Refresh Rate (DRR) * 000 = Refresh disabled * 001 = 15.6 us * 010 = 31.2 us * 011 = 62.4 us * 100 = 124.8 us * 101 = 249.6 us * 110 = Reserved * 111 = Reserved */ /* Choose SDRAM (not registered), and disable refresh for now. */ DRAMC, 0x00, 0x08, /* * PAM[6:0] - Programmable Attribute Map Registers * 0x59 - 0x5f * * 0x59 [3:0] Reserved * 0x59 [5:4] 0xF0000 - 0xFFFFF BIOS area * 0x5a [1:0] 0xC0000 - 0xC3FFF ISA add-on BIOS * 0x5a [5:4] 0xC4000 - 0xC7FFF ISA add-on BIOS * 0x5b [1:0] 0xC8000 - 0xCBFFF ISA add-on BIOS * 0x5b [5:4] 0xCC000 - 0xCFFFF ISA add-on BIOS * 0x5c [1:0] 0xD0000 - 0xD3FFF ISA add-on BIOS * 0x5c [5:4] 0xD4000 - 0xD7FFF ISA add-on BIOS * 0x5d [1:0] 0xD8000 - 0xDBFFF ISA add-on BIOS * 0x5d [5:4] 0xDC000 - 0xDFFFF ISA add-on BIOS * 0x5e [1:0] 0xE0000 - 0xE3FFF BIOS entension * 0x5e [5:4] 0xE4000 - 0xE7FFF BIOS entension * 0x5f [1:0] 0xE8000 - 0xEBFFF BIOS entension * 0x5f [5:4] 0xEC000 - 0xEFFFF BIOS entension * * Bit assignment: * 00 = DRAM Disabled (all access goes to memory mapped I/O space) * 01 = Read Only (Reads to DRAM, writes to memory mapped I/O space) * 10 = Write Only (Writes to DRAM, reads to memory mapped I/O space) * 11 = Read/Write (all access goes to DRAM) */ /* * Map all legacy regions to RAM (read/write). This is required if * you want to use the RAM area from 768 KB - 1 MB. If the PAM * registers are not set here appropriately, the RAM in that region * will not be accessible, thus a RAM check of it will also fail. * * TODO: This was set in sdram_set_spd_registers(). * Test if it still works when set here. */ PAM0, 0x00, 0x30, PAM1, 0x00, 0x33, PAM2, 0x00, 0x33, PAM3, 0x00, 0x33, PAM4, 0x00, 0x33, PAM5, 0x00, 0x33, PAM6, 0x00, 0x33, /* DRB[0:7] - DRAM Row Boundary Registers * 0x60 - 0x67 * * An array of 8 byte registers, which hold the ending memory address * assigned to each pair of DIMMs, in 8MB granularity. * * 0x60 DRB0 = Total memory in row0 (in 8 MB) * 0x61 DRB1 = Total memory in row0+1 (in 8 MB) * 0x62 DRB2 = Total memory in row0+1+2 (in 8 MB) * 0x63 DRB3 = Total memory in row0+1+2+3 (in 8 MB) * 0x64 DRB4 = Total memory in row0+1+2+3+4 (in 8 MB) * 0x65 DRB5 = Total memory in row0+1+2+3+4+5 (in 8 MB) * 0x66 DRB6 = Total memory in row0+1+2+3+4+5+6 (in 8 MB) * 0x67 DRB7 = Total memory in row0+1+2+3+4+5+6+7 (in 8 MB) */ /* Set the DRBs to zero for now, this will be fixed later. */ DRB0, 0x00, 0x00, DRB1, 0x00, 0x00, DRB2, 0x00, 0x00, DRB3, 0x00, 0x00, DRB4, 0x00, 0x00, DRB5, 0x00, 0x00, DRB6, 0x00, 0x00, DRB7, 0x00, 0x00, /* FDHC - Fixed DRAM Hole Control Register * 0x68 * * Controls two fixed DRAM holes: 512 KB - 640 KB and 15 MB - 16 MB. * * [7:6] Hole Enable (HEN) * 00 = None * 01 = 512 KB - 640 KB (128 KB) * 10 = 15 MB - 16 MB (1 MB) * 11 = Reserved * [5:0] Reserved */ /* No memory holes. */ FDHC, 0x00, 0x00, /* RPS - SDRAM Row Page Size Register * 0x74 - 0x75 * * Sets the row page size for SDRAM. For EDO memory, the page * size is fixed at 2 KB. * * [15:0] Page Size (PS) * TODO */ // TODO RPS + 0, 0x00, 0x00, RPS + 1, 0x00, 0x00, /* SDRAMC - SDRAM Control Register * 0x76 - 0x77 * * [15:10] Reserved * [09:08] Idle/Pipeline DRAM Leadoff Timing (IPDLT) * 00 = Illegal * 01 = Add a clock delay to the lead-off clock count * 10 = Illegal * 11 = Illegal * [07:05] SDRAM Mode Select (SMS) * 000 = Normal SDRAM Operation (default) * 001 = NOP Command Enable * 010 = All Banks Precharge Enable * 011 = Mode Register Set Enable * 100 = CBR Enable * 101 = Reserved * 110 = Reserved * 111 = Reserved * [04:04] SDRAMPWR * 0 = 3 DIMM configuration * 1 = 4 DIMM configuration (GCKE only) * [03:03] Leadoff Command Timing (LCT) * 0 = 4 CS# Clock * 1 = 3 CS# Clock * [02:02] CAS# Latency (CL) * 0 = 3 DCLK CAS# latency * 1 = 2 DCLK CAS# latency * [01:01] SDRAM RAS# to CAS# Delay (SRCD) * 0 = 3 clocks between a row activate and a read or write cmd. * 1 = 2 clocks between a row activate and a read or write cmd. * [00:00] SDRAM RAS# Precharge (SRP) * 0 = 3 clocks of RAS# precharge * 1 = 2 clocks of RAS# precharge */ /* TODO: Set bit 4 defaults based on config option. * Not all BX boards have 4 DIMM slots. */ SDRAMC + 0, 0x00, 0x10, /* Don't bother touching SDRAMC + 1 */ /* PGPOL - Paging Policy Register * 0x78 - 0x79 * * [15:08] Banks per Row (BPR) * 0 = 2 banks * 1 = 4 banks * [07:05] Reserved * [04:04] Intel Reserved * [03:00] DRAM Idle Timer (DIT) * 0000 = 0 clocks * 0001 = 2 clocks * 0010 = 4 clocks * 0011 = 8 clocks * 0100 = 10 clocks * 0101 = 12 clocks * 0110 = 16 clocks * 0111 = 32 clocks * 1xxx = Infinite (pages are not closed for idle condition) */ PGPOL + 0, 0x00, 0x03, PGPOL + 1, 0x00, 0xff, /* PMCR - Power Management Control Register * 0x7a * * [07:07] Power Down SDRAM Enable (PDSE) * 1 = Enable * 0 = Disable * [06:06] ACPI Control Register Enable (SCRE) * 1 = Enable * 0 = Disable (default) * [05:05] Suspend Refresh Type (SRT) * 1 = Self refresh mode * 0 = CBR fresh mode * [04:04] Normal Refresh Enable (NREF_EN) * 1 = Enable * 0 = Disable * [03:03] Quick Start Mode (QSTART) * 1 = Quick start mode for the processor is enabled * [02:02] Gated Clock Enable (GCLKEN) * 1 = Enable * 0 = Disable * [01:01] AGP Disable (AGP_DIS) * 1 = Disable * 0 = Enable * [00:00] CPU reset without PCIRST enable (CRst_En) * 1 = Enable * 0 = Disable */ PMCR, 0x00, 0x00, /* DRAMT - DRAM Timing Register (only applies to EDO) * 0x58 * * [07:02] Reserved * [01:01] EDO RASx# Wait State for row misses (RWS) * 1 = 2 tASR * 0 = 1 tASR * [00:00] EDO CASx# Wait State for page hits (CWS) * 1 = 2 Tasc * 0 = 1 Tasc */ DRAMT, 0x00, 0x03, /* Enable SCRR.SRRAEN and let BX choose the SRR. */ SCRR + 1, 0x00, 0x10, }; /*----------------------------------------------------------------------------- SDRAM configuration functions. -----------------------------------------------------------------------------*/ /** * Send the specified RAM command to all DIMMs. * * @param command The RAM command to send to the DIMM(s). */ static void do_ram_command(u32 command) { int i, caslatency; u8 dimm_start, dimm_end; u16 reg16; u32 addr, addr_offset; /* Configure the RAM command. */ reg16 = pci_read_config16(NB, SDRAMC); reg16 &= 0xff1f; /* Clear bits 7-5. */ reg16 |= (u16) (command << 5); /* Write command into bits 7-5. */ pci_write_config16(NB, SDRAMC, reg16); /* * RAM_COMMAND_NORMAL affects only the memory controller and * doesn't need to be "sent" to the DIMMs. */ if (command == RAM_COMMAND_NORMAL) return; /* Get CAS latency when executing RAM_COMMAND_MRS to program * CAS latencies into memory chips. */ caslatency = 3; if (reg16 & 0x04) { caslatency = 2; } /* Send the RAM command to each row of memory. */ dimm_start = 0; for (i = 0; i < (DIMM_SOCKETS * 2); i++) { addr_offset = 0; if (command == RAM_COMMAND_MRS) { /* * MAA[12:11,9:0] must be inverted when sent to DIMM * 2 or 3 (no inversion if sent to DIMM 0 or 1). */ if ((i >= 0 && i <= 3) && caslatency == 3) addr_offset = 0x1d0; if ((i >= 4 && i <= 7) && caslatency == 3) addr_offset = 0x1e28; if ((i >= 0 && i <= 3) && caslatency == 2) addr_offset = 0x150; if ((i >= 4 && i <= 7) && caslatency == 2) addr_offset = 0x1ea8; } dimm_end = pci_read_config8(NB, DRB + i); addr = (dimm_start * 8 * 1024 * 1024) + addr_offset; if (dimm_end > dimm_start) { #if 0 PRINT_DEBUG(" Sending RAM command 0x"); PRINT_DEBUG_HEX16(reg16); PRINT_DEBUG(" to 0x"); PRINT_DEBUG_HEX32(addr); PRINT_DEBUG("\r\n"); #endif read32(addr); } /* Set the start of the next DIMM. */ dimm_start = dimm_end; } } static void set_dram_buffer_strength(void) { /* Tally how many rows between rows 0-3 and rows 4-7 are populated. * P2B-LS vendor BIOS refers to these two tallies multiple times * in determining how to program MBFS, MBSC, among other things. */ int dimm03 = 0; int dimm47 = 0; int drb = 0; int drb1, i; for (i=DRB0; i<=DRB3; i++) { drb1 = pci_read_config8(NB, i); if (drb != drb1) { dimm03++; drb = drb1; } } drb = 0; for (i=DRB4; i<=DRB7; i++) { drb1 = pci_read_config8(NB, i); if (drb != drb1) { dimm47++; drb = drb1; } } /* Bit maps for programming MBSC[39:0] * MBSC[47:40] are reserved * a: >2 rows DIMM0-1 : else * b: >2 rows DIMM2-3 : else * c: >4 rows DIMM0-4 : else * f: fixed * 00 = 1x * 01 = invalid * 10 = 2x * 11 = 3x * 0 = 1x * 1 = 2x * * 3 32 21 10 0 * 9876543210987654321098765432109876543210 * a 10------------------------1010----------:11------------------------1111---------- * b --10--------------------------1010------:--11--------------------------1111------ * c 1011------------------------------1100--:xxxx------------------------------1011-- * f ----1010101000000000000000------------00:----1010101000000000000000------------00 * | | | | | | | | | | ||||||| | | | | | | * | | | | | | | | | | ||||||| | | | | | +- CKE0/FENA * | | | | | | | | | | ||||||| | | | | +--- CKE1/GCKE * | | | | | | | | | | ||||||| | | | +----- DQMA/CASA[764320]# * | | | | | | | | | | ||||||| | | +------- DQMB1/CASB1# * | | | | | | | | | | ||||||| | +--------- DQMB5/CASB5# * | | | | | | | | | | ||||||| +----------- DQMA1/CASA1# * | | | | | | | | | | ||||||+------------- DQMA5/CASA5# * | | | | | | | | | | ++++++-------------- CSA0-5#,CSB0-5#\ * | | | | | | | | | +--------------------- CSA6#/CKE2# \ * | | | | | | | | +----------------------- CSB6#/CKE4# + (All 2x) * | | | | | | | +------------------------- CSA7#/CKE3# / * | | | | | | +--------------------------- CSB7#/CKE5# / * | | | | | +----------------------------- MECC[7:0] #1 (2x) * | | | | +------------------------------- MECC[7:0] #2 (2x) * | | | +--------------------------------- MD[63:0] #1 (2x) * | | +----------------------------------- MD[63:0] #2 (2x) * | +------------------------------------- MAB[12:11,9:0]#,MAB[13,10],WEB#,SRASB#,SCASB# * +--------------------------------------- MAA[13:0],WEA#,SRASA#,SCASA# */ uint8_t mbsc[5]; mbsc[0] = 0; mbsc[1] = 0; mbsc[2] = 0; mbsc[3] = 0xa0; mbsc[4] = 0x0a; /* Bit maps for programming MBFS[23:0] * a: >2 rows DIMM0-1 : else * b: >2 rows DIMM2-3 : else * c: >4 rows DIMM0-4 : else * f: fixed * 0 = 66MHz * 1 = 100MHz * * 2 21 10 0 * 321098765432109876543210 * a x1---------------11-----:x0---------------00----- * b x-1----------------11---:x-0----------------00--- * c x---------------------1-:x---------------------0- * f x--1111111111111100001-0:x--1111111111111100001-0 * |||||||||||||||||||||||| * |||||||||||||||||||||||+- CKE0/FENA (66MHz) * ||||||||||||||||||||||+-- CKE1/GCKE (100MHz if >4 rows overall) * |||||||||||||||||||||+--- DQMA/CASA[764320]#\ * ||||||||||||||||||||+---- DQMB1/CASB1# \ * |||||||||||||||||||+----- DQMB5/CASB5# \(all 66MHz) * ||||||||||||||||||+------ DQMA1/CASA1# / * |||||||||||||||||+------- DQMA5/CASA5# / * |||||||||||++++++-------- CSA0-5#,CSB0-5# / * ||||||||||+-------------- CSA6#/CKE2# \ * |||||||||+--------------- CSB6#/CKE4# + (All 100MHz) * ||||||||+---------------- CSA7#/CKE3# / * |||||||+----------------- CSB7#/CKE5# / * |||||++------------------ MECC[7:0] #2/#1 (100MHz) * |||++-------------------- MD[63:0] #2/#1 (100MHz) * ||+---------------------- MAB[12:11,9:0]#,MAB[13,10],WEB#,SRASB#,SCASB# * |+----------------------- MAA[13:0],WEA#,SRASA#,SCASA# * +------------------------ Reserved */ uint8_t mbfs[3]; mbfs[0]=0x84; mbfs[1]=0xff; mbfs[2]=0x1f; i = pci_read_config8(NB, NBXCFG+1); if (dimm03 > 2) { mbsc[4] |= 0x80; mbsc[1] |= 0x28; mbfs[2] |= 0x40; mbfs[0] |= 0x60; } else { mbsc[4] |= 0xc0; mbsc[1] |= 0x3c; } if ((dimm03 + dimm47) > 4) { mbsc[4] = 0xba; mbsc[0] = 0x30; mbfs[0] |= 0x02; } else { mbsc[0] = 0x2c; } if (dimm47 > 2) { mbsc[4] |= 0x20; mbsc[1] |= 0x02; mbsc[0] |= 0x80; mbfs[2] |= 0x20; mbfs[0] |= 0x18; } else { mbsc[4] |= 0x30; mbsc[1] |= 0x03; mbsc[0] |= 0xc0; } for (i=0; i<5; i++) { pci_write_config8(NB, MBSC + i, mbsc[i]); } for (i=0; i<3; i++) { pci_write_config8(NB, MBFS + i, mbfs[i]); } } /*----------------------------------------------------------------------------- DIMM-independant configuration functions. -----------------------------------------------------------------------------*/ static void spd_enable_refresh(void) { int i, value; uint8_t reg; reg = pci_read_config8(NB, DRAMC); for (i = 0; i < DIMM_SOCKETS; i++) { value = spd_read_byte(DIMM_SPD_BASE + i, SPD_REFRESH); if (value < 0) continue; reg = (reg & 0xf8) | refresh_rate_map[(value & 0x7f)]; PRINT_DEBUG(" Enabling refresh (DRAMC = 0x"); PRINT_DEBUG_HEX8(reg); PRINT_DEBUG(") for DIMM "); PRINT_DEBUG_HEX8(i); PRINT_DEBUG("\r\n"); } pci_write_config8(NB, DRAMC, reg); } /** * Selects the fastest appropriate timing for given FSB * frequency and programs the northbridge. * * @param mhz FSB frequency in megahertz. */ /* TODO: This function only applies to SDRAM. Make one for EDO memory. */ static void set_sdram_timing(unsigned int mhz) { uint8_t reg, dimm_start, dimm_end, value, tclk, tac; int i, device, latency; /* BOLD ASSUMPTION: Take FSB, divide 1000 by it to get * clock interval in ns, double for 2DCLK latency. * If SPD latency exceeds that, use 3DCLK latency. */ latency = 2000 / mhz; /* 1000 / mhz * 2 */ /* Can we work without setting SDRAMC[9:8] to 01? */ /* pci_write_config8(NB, SDRAMC+1, 0x01);*/ /* First assume CL=2, SRCD=2, SRP=2. */ reg = pci_read_config8(NB, SDRAMC) & 0xf0 | 0x07; /* TODO: Determine correct MAA/MAB load for LCT */ /* Probe SPD on all DIMMs for the lowest CAS latency (of CL3 and CL2) with * Tclk <= 10.0ns and Tac <= 6.0ns. * If something goes wrong, assume CL3. */ dimm_start = 0; for (i = 0; i < DIMM_SOCKETS; i++) { dimm_end = pci_read_config8(NB, DRB1 + (i * 2)); device = DIMM_SPD_BASE + i; if (dimm_end > dimm_start) { value = spd_read_byte(device, SPD_ACCEPTABLE_CAS_LATENCIES) & 0x06; switch (value) { case 0x02: /* CL2 only */ tclk = spd_read_byte(device, SPD_MIN_CYCLE_TIME_AT_CAS_MAX); tac = spd_read_byte(device, SPD_ACCESS_TIME_FROM_CLOCK); break; case 0x06: /* CL3 and CL2, get tclk and tac from second highest CL */ tclk = spd_read_byte(device, SPD_SDRAM_CYCLE_TIME_2ND); tac = spd_read_byte(device, SPD_ACCESS_TIME_FROM_CLOCK_2ND); /* NOTE: For older SPD versions upper nibble having 1-3 means 16-18ns * respectively for both of above. */ break; default: tclk = 0xff; tac = 0xff; } /* Unsatisfactory tclk or tac or no data, use CL3 */ if (tclk > 0xa0 || tac > 0x60) { reg &= 0xfb; } /* These two latency values are in just nanoseconds */ value = spd_read_byte(device, SPD_tRCD); if (value > latency) { reg &= 0xfd; } value = spd_read_byte(device, SPD_tRP); if (value > latency) { reg &= 0xfe; } } dimm_start = dimm_end; } pci_write_config8(NB, SDRAMC, reg); } /* Sets DRAM attributes one DIMM at a time, based on SPD data Northbridge settings that got set here: NBXCFG[31:24] DRB0-DRB7 RPS DRAMC PGPOL */ /* These two #defines are for our use only */ #define DETECTED_EDO 0x02 #define DETECTED_SDRAM 0x04 /* Below is bitwise-or of above */ #define DETECTED_EDO_MIXED_WITH_SDRAM 0x06 static void set_dram_registers(void) { int i, dra, drb, col, width, value; uint8_t bpr, edosd, nbxecc, rps; edosd = 0; rps = 0; drb = 0; bpr = 0; nbxecc = 0xff; for (i = 0; i < DIMM_SOCKETS; i++) { unsigned device; device = DIMM_SPD_BASE + i; bpr >>= 2; nbxecc >>= 2; /* "DRA" is our RPS for the two rows on this DIMM. */ /* Set to 0 in case there's no DIMM in the slot. */ dra = 0; /* First check if a DIMM is actually present. */ value = spd_read_byte(device, SPD_MEMORY_TYPE); /* 440BX supports EDO too, but that support is TODO */ if (value == SPD_MEMORY_TYPE_EDO || value == SPD_MEMORY_TYPE_SDRAM) { PRINT_DEBUG("Found "); if (value == SPD_MEMORY_TYPE_EDO) { edosd |= DETECTED_EDO; PRINT_DEBUG("EDO "); } else if (value == SPD_MEMORY_TYPE_SDRAM) { edosd |= DETECTED_SDRAM; PRINT_DEBUG("SDRAM "); } PRINT_DEBUG("DIMM in slot "); PRINT_DEBUG_HEX8(i); PRINT_DEBUG("\r\n"); /* - Memory compatibility checks - */ /* Cannot mix EDO/SDRAM/Registered SDRAM */ if (edosd == DETECTED_EDO_MIXED_WITH_SDRAM) { print_err("Mixing EDO/SDRAM unsupported!\r\n"); die("HALT\r\n"); } /* TODO: EDO-specific memory compatibility checks * 1. 60ns only at 66MHz */ /* The 440BX supports asymmetrical dual-sided dimms (I can't test though) * but can't handle DIMMs smaller than 8MB or larger than 128MB per side. */ struct dimm_size sz = spd_get_dimm_size(device); if ((sz.side1 < 8)) { print_err("DIMMs smaller than 8MB per side are not supported on this northbridge.\r\n"); die("HALT\r\n"); } if ((sz.side1 > 128)) { print_err ("DIMMs larger than 128MB per side are not supported on this northbridge.\r\n"); die("HALT\r\n"); } /* Is this an ECC DIMM? (Actually this will be a 2 if so) */ /* TODO: Other registers than NBXCFG also needs this ECC information */ value = spd_read_byte(device, SPD_DIMM_CONFIG_TYPE); /* data width */ width = spd_read_byte(device, SPD_MODULE_DATA_WIDTH_LSB); if (value) { /* Exclude error checking data width from page size calculations */ width -= spd_read_byte(device, SPD_ERROR_CHECKING_SDRAM_WIDTH); } else { /* Without ECC, bits for these 2 banks in NBXECC should be 11. */ nbxecc |= 0xc0; } /* columns */ col = spd_read_byte(device, SPD_NUM_COLUMNS); /* calculate page size in bits */ value = ((1 << col) * width); /* convert to Kilobytes */ dra = (value >> 13); /* # of banks of DIMM (single or double sided) */ value = spd_read_byte(device, SPD_NUM_DIMM_BANKS); /* Once we have dra, col is done and can be reused, * So it's reused for number of banks. */ col = spd_read_byte(device, SPD_NUM_BANKS_PER_SDRAM); if (value == 1) { /* Second bank of 1-bank DIMMs "doesn't have ECC" - or anything. */ nbxecc |= 0x80; if (dra == 2) { dra = 0x0; /* 2KB */ } else if (dra == 4) { dra = 0x1; /* 4KB */ } else if (dra == 8) { dra = 0x2; /* 8KB */ } else { dra = -1; } /* Sets a flag in PGPOL[BPR] if this DIMM has 4 banks per row */ if (col == 4) { bpr |= 0x40; } } else if (value == 2) { if (dra == 2) { dra = 0x0; /* 2KB */ } else if (dra == 4) { dra = 0x05; /* 4KB */ } else if (dra == 8) { dra = 0x0a; /* 8KB */ } else { dra = -1; } /* Ditto */ if (col == 4) { bpr |= 0xc0; } } else { print_err("# of banks of DIMM unsupported!\r\n"); die("HALT\r\n"); } if (dra == -1) { print_err("Page size not supported\r\n"); die("HALT\r\n"); } /* - End Memory compatibility checks - */ /* We need to divide size by 8 to set up the DRB registers. */ drb += (sz.side1 / 8); /* Builds the DRB for the next row in MSB so it gets placed in DRB[n+1] * where it belongs when written as a 16-bit word. */ drb &= 0xff; drb |= (drb + (sz.side2 / 8)) << 8; } else { #if 0 PRINT_DEBUG("No DIMM found in slot "); PRINT_DEBUG_HEX8(i); PRINT_DEBUG("\r\n"); #endif /* Still have to propagate DRB over. */ drb &= 0xff; drb |= (drb << 8); } pci_write_config16(NB, DRB + (2 * i), drb); /* PRINT_DEBUG("DRB has been set to 0x"); PRINT_DEBUG_HEX16(drb); PRINT_DEBUG("\r\n"); */ /* Brings the upper DRB back down to be base for * DRB calculations for the next two rows. */ drb >>= 8; rps |= (dra & 0x0f) << (i * 4); } /* Set DRAMC[4:3] to proper memory type (EDO/SDRAM) * TODO: Account for registered SDRAM (edosd |= 0x10) */ edosd &= 0x07; if (edosd & DETECTED_SDRAM) { edosd |= 0x08; } /* Keeps only bits 3 and 4 for writing to BX. * We previously used bits 1 and 2 to log for ourselves * what memory types have been detected. */ edosd &= 0x18; /* edosd by now has been transformed to the value needed for DRAMC[4:3] */ value = pci_read_config8(NB, DRAMC) & 0xe7; value |= edosd; pci_write_config8(NB, DRAMC, value); PRINT_DEBUG("DRAMC has been set to 0x"); PRINT_DEBUG_HEX8(value); PRINT_DEBUG("\r\n"); /* Set Paging Policy Register. */ pci_write_config8(NB, PGPOL + 1, bpr); PRINT_DEBUG("PGPOL[BPR] has been set to 0x"); PRINT_DEBUG_HEX8(bpr); PRINT_DEBUG("\r\n"); /* Set DRAM Row Page Size Register. */ pci_write_config16(NB, RPS, rps); PRINT_DEBUG("RPS has been set to 0x"); PRINT_DEBUG_HEX16(rps); PRINT_DEBUG("\r\n"); /* Set NBXCFG for SDRAM rows without ECC. */ pci_write_config8(NB, NBXCFG + 3, nbxecc); PRINT_DEBUG("NBXECC[31:24] has been set to 0x"); PRINT_DEBUG_HEX8(nbxecc); PRINT_DEBUG("\r\n"); } /* Copied from i82830 northbridge code */ struct dimm_size { unsigned long side1; unsigned long side2; }; static struct dimm_size spd_get_dimm_size(unsigned int device) { struct dimm_size sz; int i, module_density, dimm_banks; sz.side1 = 0; /* Set to 0 in case it's single sided. */ sz.side2 = 0; module_density = spd_read_byte(device, SPD_DENSITY_OF_EACH_ROW_ON_MODULE); dimm_banks = spd_read_byte(device, SPD_NUM_DIMM_BANKS); /* Find the size of side1. */ /* Find the larger value. The larger value is always side1. */ /* Starts scan at 0x80 - 512MB */ for (i = 0x80; i >= 0; i >>= 1) { if ((module_density & i) == i) { sz.side1 = i; break; } } /* Test if it's a dual-sided DIMM. */ if (dimm_banks > 1) { /* Test to see if there's a second value, if so it's asymmetrical. */ if (module_density != i) { /* Find the second value, picking up where we left off. */ /* i >>= 1 done initially to make sure we don't get the same value again. */ for (i >>= 1; i >= 0; i >>= 1) { if (module_density == (sz.side1 | i)) { sz.side2 = i; break; } } } else { /* If not, it's symmetrical */ sz.side2 = sz.side1; } } /* SPD byte 31 is the memory size divided by 4 so we * need to muliply by 4 to get the total size. */ sz.side1 *= 4; sz.side2 *= 4; return sz; } /*----------------------------------------------------------------------------- Public interface. -----------------------------------------------------------------------------*/ static void northbridge_set_registers(void) { int i, max; uint8_t reg; PRINT_DEBUG("Northbridge prior to SDRAM init:\r\n"); DUMPNORTH(); max = ARRAY_SIZE(register_values); /* Set registers as specified in the register_values[] array. */ for (i = 0; i < max; i += 3) { reg = pci_read_config8(NB, register_values[i]); reg &= register_values[i + 1]; reg |= register_values[i + 2] & ~(register_values[i + 1]); pci_write_config8(NB, register_values[i], reg); #if 0 PRINT_DEBUG(" Set register 0x"); PRINT_DEBUG_HEX8(register_values[i]); PRINT_DEBUG(" to 0x"); PRINT_DEBUG_HEX8(reg); PRINT_DEBUG("\r\n"); #endif } /* TODO: Set LCT bit of SDRAMC per datasheet recommendations on 66MHz systems. */ } static void sdram_enable(void) { int i; /* 0. Wait until power/voltages and clocks are stable (200us). */ udelay(200); /* 1. Apply NOP. Wait 200 clock cycles (200us should do). */ PRINT_DEBUG("RAM Enable 1: Apply NOP\r\n"); do_ram_command(RAM_COMMAND_NOP); udelay(200); /* 2. Precharge all. Wait tRP. */ PRINT_DEBUG("RAM Enable 2: Precharge all\r\n"); do_ram_command(RAM_COMMAND_PRECHARGE); udelay(1); /* 3. Perform 8 refresh cycles. Wait tRC each time. */ PRINT_DEBUG("RAM Enable 3: CBR\r\n"); for (i = 0; i < 8; i++) { do_ram_command(RAM_COMMAND_CBR); udelay(1); } /* 4. Mode register set. Wait two memory cycles. */ PRINT_DEBUG("RAM Enable 4: Mode register set\r\n"); do_ram_command(RAM_COMMAND_MRS); udelay(2); /* 5. Normal operation. */ PRINT_DEBUG("RAM Enable 5: Normal operation\r\n"); do_ram_command(RAM_COMMAND_NORMAL); udelay(1); /* 6. Finally enable refresh. */ PRINT_DEBUG("RAM Enable 6: Enable refresh\r\n"); spd_enable_refresh(); udelay(1); } /*----------------------------------------------------------------------------- Performs all initializations required to enable RAM. @param mhz FSB frequency in megahertz. Pass 0 if unknown; it will then be inferred from what gets strapped to NBXCFG[13] and assumed to be either 100 or 66. -----------------------------------------------------------------------------*/ static void sdram_initialize(unsigned int mhz) { uint8_t reg; /* TODO: Add FSB information to function prototype and * have mainboard romstage pass this in as a param. */ unsigned int fsb = 0; /* Setup Initial SDRAM Registers */ northbridge_set_registers(); /* Setup DRAM Row Boundary Registers and other attributes. */ set_dram_registers(); set_dram_buffer_strength(); if (fsb == 0) { reg = pci_read_config8(NB, NBXCFG + 1); if ((reg & 0x30) == 0x20) { fsb = 66; } else { fsb = 100; } } set_sdram_timing(fsb); /* Currently called from mainboard romstage */ /* sdram_enable(); */ /* Enable refresh in PMCR. */ pci_write_config8(NB, PMCR, 0x10); PRINT_DEBUG("Northbridge following SDRAM init:\r\n"); DUMPNORTH(); } /* TODO: These stubs are needed to maintain compatibility with * the romstages of almost all 440BX mainboards. Change all those calls * to call just sdram_initialize(), then remove these. */ static void sdram_set_registers(void) { } static void sdram_set_spd_registers(void) { sdram_initialize(0); } /* call to sdram_enable(void) to be moved to sdram_initialize() */