Author: zbao Date: Wed Mar 10 04:43:05 2010 New Revision: 5200 URL: http://tracker.coreboot.org/trac/coreboot/changeset/5200
Log: The following patch implements Opteron Fam 10 rev D (aka Istanbul) support for coreboot. I have not updated MAX_CPUS for all fam10 mainboards, but it might make sense to multiply those by 1.5. Signed-off-by: Arne Georg Gleditsch <[email protected]> I assume the line pci_write_config32(NODE_PCI(nodeid, 0), 0x168, dword); should be put outside the loop. Everything seems to be fine. I don't have Istanbul to test. I have read every changes and they all look good. Acked-by: Zheng Bao <[email protected]> Modified: trunk/src/cpu/amd/model_10xxx/defaults.h trunk/src/cpu/amd/model_10xxx/model_10xxx_init.c trunk/src/cpu/amd/quadcore/quadcore.c trunk/src/northbridge/amd/amdfam10/northbridge.c trunk/src/northbridge/amd/amdfam10/raminit_amdmct.c trunk/src/northbridge/amd/amdmct/amddefs.h Modified: trunk/src/cpu/amd/model_10xxx/defaults.h ============================================================================== --- trunk/src/cpu/amd/model_10xxx/defaults.h Tue Mar 9 22:51:31 2010 (r5199) +++ trunk/src/cpu/amd/model_10xxx/defaults.h Wed Mar 10 04:43:05 2010 (r5200) @@ -315,44 +315,44 @@ u32 mask; } fam10_htphy_default[] = { - /* Errata 344 - Fam10 C2 + /* Errata 344 - Fam10 C2/D0 * System software should set bit 6 of F4x1[9C, 94, 8C, 84]_x[78:70, 68:60]. */ - { 0x60, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x60, AMD_RB_C2 | AMD_DA_C2 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x61, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x61, AMD_RB_C2 | AMD_DA_C2 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x62, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x62, AMD_RB_C2 | AMD_DA_C2 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x63, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x63, AMD_RB_C2 | AMD_DA_C2 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x64, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x64, AMD_RB_C2 | AMD_DA_C2 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x65, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x65, AMD_RB_C2 | AMD_DA_C2 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x66, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x66, AMD_RB_C2 | AMD_DA_C2 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x67, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x67, AMD_RB_C2 | AMD_DA_C2 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x68, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x68, AMD_RB_C2 | AMD_DA_C2 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x70, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x70, AMD_RB_C2 | AMD_DA_C2 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x71, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x71, AMD_RB_C2 | AMD_DA_C2 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x72, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x72, AMD_RB_C2 | AMD_DA_C2 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x73, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x73, AMD_RB_C2 | AMD_DA_C2 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x74, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x74, AMD_RB_C2 | AMD_DA_C2 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x75, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x75, AMD_RB_C2 | AMD_DA_C2 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x76, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x76, AMD_RB_C2 | AMD_DA_C2 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x77, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x77, AMD_RB_C2 | AMD_DA_C2 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x78, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x78, AMD_RB_C2 | AMD_DA_C2 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, /* Errata 354 - Fam10 C2 @@ -395,20 +395,20 @@ { 0x58, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - /* Errata 327 - Fam10 C2 + /* Errata 327 - Fam10 C2/D0 * BIOS should set the Link Phy Impedance Register[RttCtl] * (F4x1[9C, 94, 8C, 84]_x[D0, C0][31:29]) to 010b and * Link Phy Impedance Register[RttIndex] * (F4x1[9C, 94, 8C, 84]_x[D0, C0][20:16]) to 00100b */ - { 0xC0, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0xC0, AMD_RB_C2 | AMD_DA_C2 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x40040000, 0xe01F0000 }, - { 0xD0, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0xD0, AMD_RB_C2 | AMD_DA_C2 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x40040000, 0xe01F0000 }, - { 0x520A, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x520A, AMD_RB_C2 | AMD_DA_C2 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00004000, 0x00006000 }, /* HT_PHY_DLL_REG */ - { 0x530A, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x530A, AMD_RB_C2 | AMD_DA_C2 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00004000, 0x00006000 }, /* HT_PHY_DLL_REG */ { 0x520A, AMD_DR_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, Modified: trunk/src/cpu/amd/model_10xxx/model_10xxx_init.c ============================================================================== --- trunk/src/cpu/amd/model_10xxx/model_10xxx_init.c Tue Mar 9 22:51:31 2010 (r5199) +++ trunk/src/cpu/amd/model_10xxx/model_10xxx_init.c Wed Mar 10 04:43:05 2010 (r5200) @@ -146,6 +146,7 @@ { X86_VENDOR_AMD, 0x100F42 }, /* RB-C2 */ { X86_VENDOR_AMD, 0x100F52 }, /* BL-C2 */ { X86_VENDOR_AMD, 0x100F62 }, /* DA-C2 */ + { X86_VENDOR_AMD, 0x100F80 }, /* HY-D0 */ { 0, 0 }, }; static struct cpu_driver model_10xxx __cpu_driver = { Modified: trunk/src/cpu/amd/quadcore/quadcore.c ============================================================================== --- trunk/src/cpu/amd/quadcore/quadcore.c Tue Mar 9 22:51:31 2010 (r5199) +++ trunk/src/cpu/amd/quadcore/quadcore.c Wed Mar 10 04:43:05 2010 (r5200) @@ -29,7 +29,11 @@ u32 dword; dword = pci_read_config32(NODE_PCI(nodeid, 3), 0xe8); dword >>= 12; - dword &= 3; + /* Bit 15 is CmpCap[2] since Revision D. */ + if ((cpuid_ecx(0x80000008) & 0xff) > 3) + dword = ((dword & 8) >> 1) | (dword & 3); + else + dword &= 3; return dword; } @@ -53,7 +57,7 @@ static void real_start_other_core(u32 nodeid, u32 cores) { - u32 dword; + u32 dword, i; printk_debug("Start other core - nodeid: %02x cores: %02x\n", nodeid, cores); @@ -69,9 +73,8 @@ if(cores > 1) { dword = pci_read_config32(NODE_PCI(nodeid, 0), 0x168); - dword |= (1 << 0); // core2 - if(cores > 2) { // core3 - dword |= (1 << 1); + for (i = 0; i < cores - 1; i++) { + dword |= 1 << i; } pci_write_config32(NODE_PCI(nodeid, 0), 0x168, dword); } Modified: trunk/src/northbridge/amd/amdfam10/northbridge.c ============================================================================== --- trunk/src/northbridge/amd/amdfam10/northbridge.c Tue Mar 9 22:51:31 2010 (r5199) +++ trunk/src/northbridge/amd/amdfam10/northbridge.c Wed Mar 10 04:43:05 2010 (r5200) @@ -1364,6 +1364,8 @@ if (dev && dev->enabled) { j = pci_read_config32(dev, 0xe8); cores_found = (j >> 12) & 3; // dev is func 3 + if (siblings > 3) + cores_found |= (j >> 13) & 4; printk_debug(" %s siblings=%d\n", dev_path(dev), cores_found); } Modified: trunk/src/northbridge/amd/amdfam10/raminit_amdmct.c ============================================================================== --- trunk/src/northbridge/amd/amdfam10/raminit_amdmct.c Tue Mar 9 22:51:31 2010 (r5199) +++ trunk/src/northbridge/amd/amdfam10/raminit_amdmct.c Wed Mar 10 04:43:05 2010 (r5200) @@ -150,6 +150,9 @@ case 0x10062: ret = AMD_DA_C2; break; + case 0x10080: + ret = AMD_HY_D0; + break; default: /* FIXME: mabe we should die() here. */ print_err("FIXME! CPU Version unknown or not supported! \n"); Modified: trunk/src/northbridge/amd/amdmct/amddefs.h ============================================================================== --- trunk/src/northbridge/amd/amdmct/amddefs.h Tue Mar 9 22:51:31 2010 (r5199) +++ trunk/src/northbridge/amd/amdmct/amddefs.h Wed Mar 10 04:43:05 2010 (r5200) @@ -42,6 +42,7 @@ #define AMD_DR_B3 0x00800000 /* Barcelona B3 */ #define AMD_RB_C2 0x01000000 /* Shanghai C2 */ #define AMD_DA_C2 0x02000000 /* XXXX C2 */ +#define AMD_HY_D0 0x04000000 /* Istanbul D0 */ /* * Groups - Create as many as you wish, from the above public values @@ -59,7 +60,7 @@ #define AMD_DR_LT_B3 (AMD_DR_B0 | AMD_DR_B1 | AMD_DR_B2 | AMD_DR_BA) #define AMD_DR_GT_B0 (AMD_DR_ALL & ~(AMD_DR_B0)) #define AMD_DR_ALL (AMD_DR_Bx) -#define AMD_FAM10_ALL (AMD_DR_ALL | AMD_RB_C2) +#define AMD_FAM10_ALL (AMD_DR_ALL | AMD_RB_C2 | AMD_HY_D0) #define AMD_FAM10_GT_B0 (AMD_FAM10_ALL & ~(AMD_DR_B0)) /* -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
