This patch fixes up the i82801_lpc.c code post transition.
Boot Tested (bootlog attached)
Signed-off-by: Joseph Smith <[email protected]>
--
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org
Index: src/southbridge/intel/i82801dx/i82801dx_lpc.c
===================================================================
--- src/southbridge/intel/i82801dx/i82801dx_lpc.c (revision 5220)
+++ src/southbridge/intel/i82801dx/i82801dx_lpc.c (working copy)
@@ -4,6 +4,7 @@
* Copyright (C) 2003 Linux Networx
* Copyright (C) 2004 SuSE Linux AG
* Copyright (C) 2004 Tyan Computer
+ * Copyright (C) 2010 Joseph Smith <[email protected]>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
@@ -30,169 +31,207 @@
#include <arch/io.h>
#include "i82801dx.h"
+#define GPIO_BASE_ADDR 0x00000500 /* GPIO Base Address Register */
+
#define NMI_OFF 0
-void i82801dx_enable_ioapic(struct device *dev)
+typedef struct southbridge_intel_i82801dx_config config_t;
+
+void i82801dx_enable_apic(struct device *dev)
{
- u32 dword;
- volatile u32 *ioapic_sba = (volatile u32 *)0xfec00000;
- volatile u32 *ioapic_sbd = (volatile u32 *)0xfec00010;
+ uint32_t reg32;
+ volatile uint32_t *ioapic_index = (volatile uint32_t *)0xfec00000;
+ volatile uint32_t *ioapic_data = (volatile uint32_t *)0xfec00010;
- dword = pci_read_config32(dev, GEN_CNTL);
- dword |= (3 << 7); /* enable ioapic */
- dword |= (1 << 13); /* coprocessor error enable */
- dword |= (1 << 1); /* delay transaction enable */
- dword |= (1 << 2); /* DMA collection buf enable */
- pci_write_config32(dev, GEN_CNTL, dword);
- printk_debug("ioapic southbridge enabled %x\n", dword);
- *ioapic_sba = 0;
- *ioapic_sbd = (2 << 24);
- //lyh *ioapic_sba=3;
- //lyh *ioapic_sbd=1;
- *ioapic_sba = 0;
- dword = *ioapic_sbd;
- printk_debug("Southbridge apic id = %x\n", dword);
- if (dword != (2 << 24))
- die("");
- //lyh *ioapic_sba=3;
- //lyh dword=*ioapic_sbd;
- //lyh printk_debug("Southbridge apic DT = %x\n",dword);
- //lyh if(dword!=1)
- //lyh die("");
+ /* Set ACPI base address (I/O space). */
+ pci_write_config32(dev, PMBASE, (PMBASE_ADDR | 1));
+ /* Enable ACPI I/O and power management. */
+ pci_write_config8(dev, ACPI_CNTL, 0x10);
+
+ reg32 = pci_read_config32(dev, GEN_CNTL);
+ reg32 |= (3 << 7); /* Enable IOAPIC */
+ reg32 |= (1 << 13); /* Coprocessor error enable */
+ reg32 |= (1 << 1); /* Delayed transaction enable */
+ reg32 |= (1 << 2); /* DMA collection buffer enable */
+ pci_write_config32(dev, GEN_CNTL, reg32);
+ printk_debug("IOAPIC Southbridge enabled %x\n", reg32);
+
+ *ioapic_index = 0;
+ *ioapic_data = (1 << 25);
+
+ *ioapic_index = 0;
+ reg32 = *ioapic_data;
+ printk_debug("Southbridge APIC ID = %x\n", reg32);
+ if (reg32 != (1 << 25))
+ die("APIC Error\n");
+
+ /* TODO: From i82801ca, needed/useful on other ICH? */
+ *ioapic_index = 3; /* Select Boot Configuration register. */
+ *ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */
}
void i82801dx_enable_serial_irqs(struct device *dev)
{
+ /* Set packet length and toggle silent mode bit. */
pci_write_config8(dev, SERIRQ_CNTL,
(1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0));
+ pci_write_config8(dev, SERIRQ_CNTL,
+ (1 << 7) | (0 << 6) | ((21 - 17) << 2) | (0 << 0));
}
-void i82801dx_lpc_route_dma(struct device *dev, u8 mask)
+static void i82801dx_pirq_init(device_t dev)
{
- u16 word;
- int i;
- word = pci_read_config16(dev, PCI_DMA_CFG);
- word &= ((1 << 10) - (1 << 8));
- for (i = 0; i < 8; i++) {
- if (i == 4)
- continue;
- word |= ((mask & (1 << i)) ? 3 : 1) << (i * 2);
+ /* Get the chip configuration */
+ config_t *config = dev->chip_info;
+
+ pci_write_config8(dev, PIRQA_ROUT, config->pirqa_routing);
+ pci_write_config8(dev, PIRQB_ROUT, config->pirqb_routing);
+ pci_write_config8(dev, PIRQC_ROUT, config->pirqc_routing);
+ pci_write_config8(dev, PIRQD_ROUT, config->pirqd_routing);
+ pci_write_config8(dev, PIRQE_ROUT, config->pirqe_routing);
+ pci_write_config8(dev, PIRQF_ROUT, config->pirqf_routing);
+ pci_write_config8(dev, PIRQG_ROUT, config->pirqg_routing);
+ pci_write_config8(dev, PIRQH_ROUT, config->pirqh_routing);
+
+}
+
+static void i82801dx_power_options(device_t dev)
+{
+ uint8_t byte;
+ int pwr_on = -1;
+ int nmi_option;
+
+ /* power after power fail */
+ /* FIXME this doesn't work! */
+ /* Which state do we want to goto after g3 (power restored)?
+ * 0 == S0 Full On
+ * 1 == S5 Soft Off
+ */
+ pci_write_config8(dev, GEN_PMCON_3, pwr_on ? 0 : 1);
+ printk_info("Set power %s if power fails\n", pwr_on ? "on" : "off");
+
+ /* Set up NMI on errors. */
+ byte = inb(0x61);
+ byte &= ~(1 << 3); /* IOCHK# NMI Enable */
+ byte &= ~(1 << 2); /* PCI SERR# Enable */
+ outb(byte, 0x61);
+ byte = inb(0x70);
+
+ nmi_option = NMI_OFF;
+ get_option(&nmi_option, "nmi");
+ if (nmi_option) {
+ byte &= ~(1 << 7); /* Set NMI. */
+ outb(byte, 0x70);
}
- pci_write_config16(dev, PCI_DMA_CFG, word);
}
+static void gpio_init(device_t dev)
+{
+ pci_write_config32(dev, GPIO_BASE, (GPIO_BASE_ADDR | 1));
+ pci_write_config8(dev, GPIO_CNTL, 0x10);
+}
+
void i82801dx_rtc_init(struct device *dev)
{
- u8 byte;
- u32 dword;
+ uint8_t reg8;
+ uint32_t reg32;
int rtc_failed;
- byte = pci_read_config8(dev, GEN_PMCON_3);
- rtc_failed = byte & RTC_FAILED;
+
+ reg8 = pci_read_config8(dev, GEN_PMCON_3);
+ rtc_failed = reg8 & RTC_BATTERY_DEAD;
if (rtc_failed) {
- byte &= ~(1 << 1); /* preserve the power fail state */
- pci_write_config8(dev, GEN_PMCON_3, byte);
+ reg8 &= ~(1 << 1); /* Preserve the power fail state. */
+ pci_write_config8(dev, GEN_PMCON_3, reg8);
}
- dword = pci_read_config32(dev, GEN_STS);
- rtc_failed |= dword & (1 << 2);
+ reg32 = pci_read_config32(dev, GEN_STS);
+ rtc_failed |= reg32 & (1 << 2);
rtc_init(rtc_failed);
-}
-void i82801dx_1f0_misc(struct device *dev)
-{
- pci_write_config16(dev, PCICMD, 0x014f);
- pci_write_config32(dev, PMBASE, 0x00001001);
- pci_write_config8(dev, ACPI_CNTL, 0x10);
- pci_write_config32(dev, GPIO_BASE, 0x00001181);
- pci_write_config8(dev, GPIO_CNTL, 0x10);
- pci_write_config32(dev, PIRQA_ROUT, 0x0A05030B);
- pci_write_config8(dev, PIRQE_ROUT, 0x07);
+ /* Enable access to the upper 128 byte bank of CMOS RAM. */
pci_write_config8(dev, RTC_CONF, 0x04);
- pci_write_config8(dev, COM_DEC, 0x10); //lyh E0->
- pci_write_config16(dev, LPC_EN, 0x000F); //LYH 000D->
}
-static void enable_hpet(struct device *dev)
+void i82801dx_lpc_route_dma(struct device *dev, uint8_t mask)
{
- const unsigned long hpet_address = 0xfed0000;
+ uint16_t reg16;
+ int i;
- u32 dword;
- u32 code = (0 & 0x3);
+ reg16 = pci_read_config16(dev, PCI_DMA_CFG);
+ reg16 &= 0x300;
+ for (i = 0; i < 8; i++) {
+ if (i == 4)
+ continue;
+ reg16 |= ((mask & (1 << i)) ? 3 : 1) << (i * 2);
+ }
+ pci_write_config16(dev, PCI_DMA_CFG, reg16);
+}
- dword = pci_read_config32(dev, GEN_CNTL);
- dword |= (1 << 17); /* enable hpet */
- /*Bits [16:15]Memory Address Range
- 00 FED0_0000h - FED0_03FFh
- 01 FED0_1000h - FED0_13FFh
- 10 FED0_2000h - FED0_23FFh
- 11 FED0_3000h - FED0_33FFh */
+static void i82801dx_lpc_decode_en(device_t dev)
+{
+ /* Decode 0x3F8-0x3FF (COM1) for COMA port, 0x2F8-0x2FF (COM2) for COMB.
+ * LPT decode defaults to 0x378-0x37F and 0x778-0x77F.
+ * Floppy decode defaults to 0x3F0-0x3F5, 0x3F7.
+ * We also need to set the value for LPC I/F Enables Register.
+ */
+ pci_write_config8(dev, COM_DEC, 0x10);
+ pci_write_config16(dev, LPC_EN, 0x300F);
+}
- dword &= ~(3 << 15); /* clear it */
- dword |= (code << 15);
+static void enable_hpet(struct device *dev)
+{
+#ifdef HPET_PRESENT
+ uint32_t reg32;
+ uint32_t code = (0 & 0x3);
- printk_debug("enabling HPET @0x%x\n", hpet_address | (code << 12));
+ reg32 = pci_read_config32(dev, GEN_CNTL);
+ reg32 |= (1 << 17); /* Enable HPET. */
+ /*
+ * Bits [16:15] Memory Address Range
+ * 00 FED0_0000h - FED0_03FFh
+ * 01 FED0_1000h - FED0_13FFh
+ * 10 FED0_2000h - FED0_23FFh
+ * 11 FED0_3000h - FED0_33FFh
+ */
+ reg32 &= ~(3 << 15); /* Clear it */
+ reg32 |= (code << 15);
+ /* TODO: reg32 is never written to anywhere? */
+ printk_debug("Enabling HPET @0x%x\n", HPET_ADDR | (code << 12));
+#endif
}
static void lpc_init(struct device *dev)
{
- u8 byte;
- int pwr_on = -1;
- int nmi_option;
+ /* Set the value for PCI command register. */
+ pci_write_config16(dev, PCI_COMMAND, 0x000f);
- /* IO APIC initialization */
- i82801dx_enable_ioapic(dev);
+ /* IO APIC initialization. */
+ i82801dx_enable_apic(dev);
i82801dx_enable_serial_irqs(dev);
-#ifdef SUSPICIOUS_LOOKING_CODE
- // The ICH-4 datasheet does not mention this configuration register.
- // This code may have been inherited (incorrectly) from code for the AMD 766 southbridge,
- // which *does* support this functionality.
+ /* Setup the PIRQ. */
+ i82801dx_pirq_init(dev);
- /* posted memory write enable */
- byte = pci_read_config8(dev, 0x46);
- pci_write_config8(dev, 0x46, byte | (1 << 0));
-#endif
+ /* Setup power options. */
+ i82801dx_power_options(dev);
- /* power after power fail */
- /* FIXME this doesn't work! */
- /* Which state do we want to goto after g3 (power restored)?
- * 0 == S0 Full On
- * 1 == S5 Soft Off
- */
- pci_write_config8(dev, GEN_PMCON_3, pwr_on ? 0 : 1);
- printk_info("set power %s after power fail\n", pwr_on ? "on" : "off");
-#if 0
- /* Enable Error reporting */
- /* Set up sync flood detected */
- byte = pci_read_config8(dev, 0x47);
- byte |= (1 << 1);
- pci_write_config8(dev, 0x47, byte);
-#endif
+ /* Set the state of the GPIO lines. */
+ gpio_init(dev);
- /* Set up NMI on errors */
- byte = inb(0x61);
- byte &= ~(1 << 3); /* IOCHK# NMI Enable */
- byte &= ~(1 << 2); /* PCI SERR# Enable */
- outb(byte, 0x61);
- byte = inb(0x70);
- nmi_option = NMI_OFF;
- get_option(&nmi_option, "nmi");
- if (nmi_option) {
- byte &= ~(1 << 7); /* set NMI */
- outb(byte, 0x70);
- }
-
- /* Initialize the real time clock */
+ /* Initialize the real time clock. */
i82801dx_rtc_init(dev);
+ /* Route DMA. */
i82801dx_lpc_route_dma(dev, 0xff);
- /* Initialize isa dma */
+ /* Initialize ISA DMA. */
isa_dma_init();
- i82801dx_1f0_misc(dev);
- /* Initialize the High Precision Event Timers */
+ /* Setup decode ports and LPC I/F enables. */
+ i82801dx_lpc_decode_en(dev);
+
+ /* Initialize the High Precision Event Timers, if present. */
enable_hpet(dev);
}
@@ -208,15 +247,15 @@
res->base = 0;
res->size = 0x1000;
res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
- IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+ IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
res->base = 0xff800000;
- res->size = 0x00800000; /* 8 MB for flash */
+ res->size = 0x00800000; /* 8 MB for flash */
res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
- IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+ IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
- res = new_resource(dev, 3); /* IOAPIC */
+ res = new_resource(dev, 3); /* IOAPIC */
res->base = 0xfec00000;
res->size = 0x00001000;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
@@ -229,12 +268,12 @@
}
static struct device_operations lpc_ops = {
- .read_resources = i82801dx_lpc_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = i82801dx_lpc_enable_resources,
- .init = lpc_init,
- .scan_bus = scan_static_bus,
- .enable = i82801dx_enable,
+ .read_resources = i82801dx_lpc_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = i82801dx_lpc_enable_resources,
+ .init = lpc_init,
+ .scan_bus = scan_static_bus,
+ .enable = i82801dx_enable,
};
/* 82801DB/DBL */
Index: src/southbridge/intel/i82801dx/i82801dx.h
===================================================================
--- src/southbridge/intel/i82801dx/i82801dx.h (revision 5220)
+++ src/southbridge/intel/i82801dx/i82801dx.h (working copy)
@@ -77,8 +77,14 @@
#define BIOS_CNTL 0x4E
#define GPIO_BASE 0x58
#define GPIO_CNTL 0x5C
-#define PIRQA_ROUT 0x60
-#define PIRQE_ROUT 0x68
+#define PIRQA_ROUT 0x60
+#define PIRQB_ROUT 0x61
+#define PIRQC_ROUT 0x62
+#define PIRQD_ROUT 0x63
+#define PIRQE_ROUT 0x68
+#define PIRQF_ROUT 0x69
+#define PIRQG_ROUT 0x6A
+#define PIRQH_ROUT 0x6B
#define COM_DEC 0xE0
#define LPC_EN 0xE6
#define FUNC_DIS 0xF2
@@ -190,4 +196,9 @@
#define TCOBASE 0x60 /* TCO Base Address Register */
#define TCO1_CNT 0x08 /* TCO1 Control Register */
+/* GEN_PMCON_3 bits */
+#define RTC_BATTERY_DEAD (1 << 2)
+#define RTC_POWER_FAILED (1 << 1)
+#define SLEEP_AFTER_POWER_FAIL (1 << 0)
+
#endif /* I82801DX_H */
coreboot-4.0-r5220M Tue Mar 16 00:57:38 EDT 2010 starting...
SMBus controller enabled
Found DIMM in slot 00
DIMM is 0x0100 on side 1
DIMM is 0x0100 on side 2
Found DIMM in slot 01
DIMM is 0x0040 on side 1
DIMM is 0x0000 on side 2
Found DIMM in slot 00, setting DRA...
Found DIMM in slot 01, setting DRA...
Initializing SDRAM Row 00
Initializing SDRAM Row 01
Initializing SDRAM Row 02
Copying coreboot to RAM.
Loading stage image.
Check CBFS header at fffeffe0
magic is 4f524243
Found CBFS header at fffeffe0
Check fallback/coreboot_ram
Stage: loading fallback/coreboot_ram @ 0x100000 (180224 bytes), entry @ 0x100000
Stage: done loading.
Jumping to image.
coreboot-4.0-r5220M Tue Mar 16 00:57:38 EDT 2010 booting...
Calibrating delay loop...
end 72e71cbc, start 2918ba08
32-bit delta 1180
calibrate_tsc 32-bit result is 1180
clocks_per_usec: 1180
Enumerating buses...
Show all devs...Before Device Enumeration.
Root Device: enabled 1, 0 resources
APIC_CLUSTER: 0: enabled 1, 0 resources
APIC: 00: enabled 1, 0 resources
PCI_DOMAIN: 0000: enabled 1, 0 resources
PCI: 00:00.0: enabled 1, 0 resources
PCI: 00:02.0: enabled 1, 0 resources
PCI: 00:1d.0: enabled 1, 0 resources
PCI: 00:1d.1: enabled 1, 0 resources
PCI: 00:1d.2: enabled 1, 0 resources
PCI: 00:1d.7: enabled 1, 0 resources
PCI: 00:1e.0: enabled 1, 0 resources
PCI: 00:1f.0: enabled 1, 0 resources
PNP: 002e.0: enabled 0, 3 resources
PNP: 002e.3: enabled 1, 3 resources
PNP: 002e.4: enabled 1, 2 resources
PNP: 002e.5: enabled 1, 2 resources
PNP: 002e.7: enabled 1, 4 resources
PNP: 002e.9: enabled 0, 0 resources
PNP: 002e.a: enabled 1, 1 resources
PNP: 002e.b: enabled 0, 0 resources
PCI: 00:1f.1: enabled 1, 0 resources
PCI: 00:1f.3: enabled 1, 0 resources
PCI: 00:1f.5: enabled 1, 0 resources
PCI: 00:1f.6: enabled 0, 0 resources
Compare with tree...
Root Device: enabled 1, 0 resources
APIC_CLUSTER: 0: enabled 1, 0 resources
APIC: 00: enabled 1, 0 resources
PCI_DOMAIN: 0000: enabled 1, 0 resources
PCI: 00:00.0: enabled 1, 0 resources
PCI: 00:02.0: enabled 1, 0 resources
PCI: 00:1d.0: enabled 1, 0 resources
PCI: 00:1d.1: enabled 1, 0 resources
PCI: 00:1d.2: enabled 1, 0 resources
PCI: 00:1d.7: enabled 1, 0 resources
PCI: 00:1e.0: enabled 1, 0 resources
PCI: 00:1f.0: enabled 1, 0 resources
PNP: 002e.0: enabled 0, 3 resources
PNP: 002e.3: enabled 1, 3 resources
PNP: 002e.4: enabled 1, 2 resources
PNP: 002e.5: enabled 1, 2 resources
PNP: 002e.7: enabled 1, 4 resources
PNP: 002e.9: enabled 0, 0 resources
PNP: 002e.a: enabled 1, 1 resources
PNP: 002e.b: enabled 0, 0 resources
PCI: 00:1f.1: enabled 1, 0 resources
PCI: 00:1f.3: enabled 1, 0 resources
PCI: 00:1f.5: enabled 1, 0 resources
PCI: 00:1f.6: enabled 0, 0 resources
scan_static_bus for Root Device
APIC_CLUSTER: 0 enabled
Finding PCI configuration type.
PCI: Using configuration type 1
PCI_DOMAIN: 0000 enabled
PCI_DOMAIN: 0000 scanning...
PCI: pci_scan_bus for bus 00
PCI: 00:00.0 [8086/3575] ops
PCI: 00:00.0 [8086/3575] enabled
PCI: 00:01.0, bad id 0xffffffff
PCI: 00:02.0 [8086/3577] ops
PCI: 00:02.0 [8086/3577] enabled
PCI: 00:03.0, bad id 0xffffffff
PCI: 00:04.0, bad id 0xffffffff
PCI: 00:05.0, bad id 0xffffffff
PCI: 00:06.0, bad id 0xffffffff
PCI: 00:07.0, bad id 0xffffffff
PCI: 00:08.0, bad id 0xffffffff
PCI: 00:09.0, bad id 0xffffffff
PCI: 00:0a.0, bad id 0xffffffff
PCI: 00:0b.0, bad id 0xffffffff
PCI: 00:0c.0, bad id 0xffffffff
PCI: 00:0d.0, bad id 0xffffffff
PCI: 00:0e.0, bad id 0xffffffff
PCI: 00:0f.0, bad id 0xffffffff
PCI: 00:10.0, bad id 0xffffffff
PCI: 00:11.0, bad id 0xffffffff
PCI: 00:12.0, bad id 0xffffffff
PCI: 00:13.0, bad id 0xffffffff
PCI: 00:14.0, bad id 0xffffffff
PCI: 00:15.0, bad id 0xffffffff
PCI: 00:16.0, bad id 0xffffffff
PCI: 00:17.0, bad id 0xffffffff
PCI: 00:18.0, bad id 0xffffffff
PCI: 00:19.0, bad id 0xffffffff
PCI: 00:1a.0, bad id 0xffffffff
PCI: 00:1b.0, bad id 0xffffffff
PCI: 00:1c.0, bad id 0xffffffff
PCI: 00:1d.0 [8086/24c2] ops
PCI: 00:1d.0 [8086/24c2] enabled
PCI: 00:1d.1 [8086/24c4] ops
PCI: 00:1d.1 [8086/24c4] enabled
PCI: 00:1d.2 [8086/24c7] ops
PCI: 00:1d.2 [8086/24c7] enabled
PCI: 00:1d.3, bad id 0xffffffff
PCI: 00:1d.4, bad id 0xffffffff
PCI: 00:1d.5, bad id 0xffffffff
PCI: 00:1d.6, bad id 0xffffffff
PCI: 00:1d.7 [8086/24cd] ops
PCI: 00:1d.7 [8086/24cd] enabled
PCI: 00:1e.0 [8086/244e] enabled
PCI: 00:1f.0 [8086/24c0] bus ops
PCI: 00:1f.0 [8086/24c0] enabled
PCI: 00:1f.1 [8086/24cb] ops
PCI: 00:1f.1 [8086/24cb] enabled
PCI: 00:1f.2, bad id 0xffffffff
PCI: 00:1f.3 [8086/24c3] enabled
PCI: 00:1f.4, bad id 0xffffffff
PCI: 00:1f.5 [8086/24c5] ops
PCI: 00:1f.5 [8086/24c5] enabled
PCI: 00:1f.7, bad id 0xffffffff
do_pci_scan_bridge for PCI: 00:1e.0
PCI: pci_scan_bus for bus 01
PCI: 01:00.0, bad id 0xffffffff
PCI: 01:01.0, bad id 0xffffffff
PCI: 01:02.0, bad id 0xffffffff
PCI: 01:03.0, bad id 0xffffffff
PCI: 01:04.0, bad id 0xffffffff
PCI: 01:05.0, bad id 0xffffffff
PCI: 01:06.0, bad id 0xffffffff
PCI: 01:07.0, bad id 0xffffffff
malloc Enter, size 1092, free_mem_ptr 00128000
malloc 00128000
PCI: 01:08.0 [8086/103a] enabled
PCI: 01:09.0, bad id 0xffffffff
PCI: 01:0a.0, bad id 0xffffffff
PCI: 01:0b.0, bad id 0xffffffff
PCI: 01:0c.0, bad id 0xffffffff
PCI: 01:0d.0, bad id 0xffffffff
PCI: 01:0e.0, bad id 0xffffffff
PCI: 01:0f.0, bad id 0xffffffff
PCI: 01:10.0, bad id 0xffffffff
PCI: 01:11.0, bad id 0xffffffff
PCI: 01:12.0, bad id 0xffffffff
PCI: 01:13.0, bad id 0xffffffff
PCI: 01:14.0, bad id 0xffffffff
PCI: 01:15.0, bad id 0xffffffff
PCI: 01:16.0, bad id 0xffffffff
PCI: 01:17.0, bad id 0xffffffff
PCI: 01:18.0, bad id 0xffffffff
PCI: 01:19.0, bad id 0xffffffff
PCI: 01:1a.0, bad id 0xffffffff
PCI: 01:1b.0, bad id 0xffffffff
PCI: 01:1c.0, bad id 0xffffffff
PCI: 01:1d.0, bad id 0xffffffff
PCI: 01:1e.0, bad id 0xffffffff
PCI: 01:1f.0, bad id 0xffffffff
PCI: pci_scan_bus returning with max=001
do_pci_scan_bridge returns max 1
scan_static_bus for PCI: 00:1f.0
Found SMSC Super I/O (ID=0x60, rev=0x01)
PNP: 002e.0 disabled
PNP: 002e.3 enabled
PNP: 002e.4 enabled
PNP: 002e.5 enabled
PNP: 002e.7 enabled
PNP: 002e.9 disabled
PNP: 002e.a enabled
PNP: 002e.b disabled
scan_static_bus for PCI: 00:1f.0 done
PCI: pci_scan_bus returning with max=001
scan_static_bus for Root Device done
done
Setting up VGA for PCI: 00:02.0
Setting PCI_BRIDGE_CTL_VGA for bridge PCI_DOMAIN: 0000
Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
Allocating resources...
Reading resources...
Root Device read_resources bus 0 link: 0
APIC_CLUSTER: 0 read_resources bus 0 link: 0
APIC: 00 missing read_resources
APIC_CLUSTER: 0 read_resources bus 0 link: 0 done
PCI_DOMAIN: 0000 read_resources bus 0 link: 0
PCI: 00:00.0 register 10(00000008), read-only ignoring it
PCI: 00:1e.0 read_resources bus 1 link: 0
PCI: 00:1e.0 read_resources bus 1 link: 0 done
PCI: 00:1f.0 read_resources bus 0 link: 0
PCI: 00:1f.0 read_resources bus 0 link: 0 done
PCI: 00:1f.5 register 10(00000001), read-only ignoring it
PCI: 00:1f.5 register 14(00000001), read-only ignoring it
PCI_DOMAIN: 0000 read_resources bus 0 link: 0 done
Root Device read_resources bus 0 link: 0 done
Done reading resources.
Show resources in subtree (Root Device)...After reading.
Root Device links 1 child on link 0 APIC_CLUSTER: 0
APIC_CLUSTER: 0 links 1 child on link 0 APIC: 00
APIC: 00 links 0 child on link 0 NULL
PCI_DOMAIN: 0000 links 1 child on link 0 PCI: 00:00.0
PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags
40040100 index 10000000
PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags
40040200 index 10000100
PCI: 00:00.0 links 0 child on link 0 NULL
PCI: 00:02.0 links 0 child on link 0 NULL
PCI: 00:02.0 resource base 0 size 4000000 align 26 gran 26 limit ffffffff
flags 1200 index 10
PCI: 00:02.0 resource base 0 size 80000 align 19 gran 19 limit ffffffff
flags 200 index 14
PCI: 00:1d.0 links 0 child on link 0 NULL
PCI: 00:1d.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100
index 20
PCI: 00:1d.1 links 0 child on link 0 NULL
PCI: 00:1d.1 resource base 0 size 20 align 5 gran 5 limit ffff flags 100
index 20
PCI: 00:1d.2 links 0 child on link 0 NULL
PCI: 00:1d.2 resource base 0 size 20 align 5 gran 5 limit ffff flags 100
index 20
PCI: 00:1d.7 links 0 child on link 0 NULL
PCI: 00:1d.7 resource base 0 size 400 align 10 gran 10 limit ffffffff flags
200 index 10
PCI: 00:1e.0 links 1 child on link 0 PCI: 01:08.0
PCI: 00:1e.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102
index 1c
PCI: 00:1e.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags
81202 index 24
PCI: 00:1e.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags
80202 index 20
PCI: 01:08.0 links 0 child on link 0 NULL
PCI: 01:08.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff
flags 200 index 10
PCI: 01:08.0 resource base 0 size 40 align 6 gran 6 limit ffff flags 100
index 14
PCI: 00:1f.0 links 1 child on link 0 PNP: 002e.0
PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100
index 10000000
PCI: 00:1f.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags
c0040200 index 10000100
PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags
c0000200 index 3
PNP: 002e.0 links 0 child on link 0 NULL
PNP: 002e.0 resource base 3f0 size 8 align 3 gran 3 limit 7ff flags
c0000100 index 60
PNP: 002e.0 resource base 6 size 1 align 0 gran 0 limit 0 flags c0000400
index 70
PNP: 002e.0 resource base 2 size 1 align 0 gran 0 limit 0 flags c0000800
index 74
PNP: 002e.3 links 0 child on link 0 NULL
PNP: 002e.3 resource base 378 size 8 align 3 gran 3 limit 7ff flags
c0000100 index 60
PNP: 002e.3 resource base 7 size 1 align 0 gran 0 limit 0 flags c0000400
index 70
PNP: 002e.3 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000800
index 74
PNP: 002e.4 links 0 child on link 0 NULL
PNP: 002e.4 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags
c0000100 index 60
PNP: 002e.4 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000400
index 70
PNP: 002e.5 links 0 child on link 0 NULL
PNP: 002e.5 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags
c0000100 index 60
PNP: 002e.5 resource base 3 size 1 align 0 gran 0 limit 0 flags c0000400
index 70
PNP: 002e.7 links 0 child on link 0 NULL
PNP: 002e.7 resource base 60 size 1 align 0 gran 0 limit ffffffff flags
c0000100 index 60
PNP: 002e.7 resource base 64 size 1 align 0 gran 0 limit ffffffff flags
c0000100 index 62
PNP: 002e.7 resource base 1 size 1 align 0 gran 0 limit 0 flags c0000400
index 70
PNP: 002e.7 resource base c size 1 align 0 gran 0 limit 0 flags c0000400
index 72
PNP: 002e.9 links 0 child on link 0 NULL
PNP: 002e.a links 0 child on link 0 NULL
PNP: 002e.a resource base 800 size 0 align 0 gran 0 limit 0 flags c0000100
index 60
PNP: 002e.b links 0 child on link 0 NULL
PCI: 00:1f.1 links 0 child on link 0 NULL
PCI: 00:1f.1 resource base 0 size 8 align 3 gran 3 limit ffff flags 100
index 10
PCI: 00:1f.1 resource base 0 size 4 align 2 gran 2 limit ffff flags 100
index 14
PCI: 00:1f.1 resource base 0 size 8 align 3 gran 3 limit ffff flags 100
index 18
PCI: 00:1f.1 resource base 0 size 4 align 2 gran 2 limit ffff flags 100
index 1c
PCI: 00:1f.1 resource base 0 size 10 align 4 gran 4 limit ffff flags 100
index 20
PCI: 00:1f.1 resource base 0 size 400 align 10 gran 10 limit ffffffff flags
200 index 24
PCI: 00:1f.3 links 0 child on link 0 NULL
PCI: 00:1f.3 resource base 0 size 20 align 5 gran 5 limit ffff flags 100
index 20
PCI: 00:1f.5 links 0 child on link 0 NULL
PCI: 00:1f.5 resource base 0 size 200 align 9 gran 9 limit ffffffff flags
200 index 18
PCI: 00:1f.5 resource base 0 size 100 align 8 gran 8 limit ffffffff flags
200 index 1c
PCI: 00:1f.6 links 0 child on link 0 NULL
PCI_DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit:
ffff
PCI: 00:1e.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit:
ffff
PCI: 01:08.0 14 * [0x0 - 0x3f] io
PCI: 00:1e.0 compute_resources_io: base: 40 size: 1000 align: 12 gran: 12
limit: ffff done
PCI: 00:1e.0 1c * [0x0 - 0xfff] io
PCI: 00:1d.0 20 * [0x1000 - 0x101f] io
PCI: 00:1d.1 20 * [0x1020 - 0x103f] io
PCI: 00:1d.2 20 * [0x1040 - 0x105f] io
PCI: 00:1f.3 20 * [0x1060 - 0x107f] io
PCI: 00:1f.1 20 * [0x1080 - 0x108f] io
PCI: 00:1f.1 10 * [0x1090 - 0x1097] io
PCI: 00:1f.1 18 * [0x1098 - 0x109f] io
PCI: 00:1f.1 14 * [0x10a0 - 0x10a3] io
PCI: 00:1f.1 1c * [0x10a4 - 0x10a7] io
PCI_DOMAIN: 0000 compute_resources_io: base: 10a8 size: 10a8 align: 12 gran: 0
limit: ffff done
PCI_DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0 limit:
ffffffff
PCI: 00:1e.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20
limit: ffffffff
PCI: 00:1e.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20
limit: ffffffff done
PCI: 00:1e.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit:
ffffffff
PCI: 01:08.0 10 * [0x0 - 0xfff] mem
PCI: 00:1e.0 compute_resources_mem: base: 1000 size: 100000 align: 20 gran: 20
limit: ffffffff done
PCI: 00:02.0 10 * [0x0 - 0x3ffffff] prefmem
PCI: 00:1e.0 20 * [0x4000000 - 0x40fffff] mem
PCI: 00:02.0 14 * [0x4100000 - 0x417ffff] mem
PCI: 00:1d.7 10 * [0x4180000 - 0x41803ff] mem
PCI: 00:1f.1 24 * [0x4180400 - 0x41807ff] mem
PCI: 00:1f.5 18 * [0x4180800 - 0x41809ff] mem
PCI: 00:1f.5 1c * [0x4180a00 - 0x4180aff] mem
PCI_DOMAIN: 0000 compute_resources_mem: base: 4180b00 size: 4180b00 align: 26
gran: 0 limit: ffffffff done
avoid_fixed_resources: PCI_DOMAIN: 0000
avoid_fixed_resources:@PCI_DOMAIN: 0000 10000000 limit 0000ffff
avoid_fixed_resources:@PCI_DOMAIN: 0000 10000100 limit ffffffff
constrain_resources: PCI_DOMAIN: 0000
constrain_resources: PCI: 00:00.0
constrain_resources: PCI: 00:02.0
constrain_resources: PCI: 00:1d.0
constrain_resources: PCI: 00:1d.1
constrain_resources: PCI: 00:1d.2
constrain_resources: PCI: 00:1d.7
constrain_resources: PCI: 00:1e.0
constrain_resources: PCI: 01:08.0
constrain_resources: PCI: 00:1f.0
constrain_resources: PNP: 002e.3
constrain_resources: PNP: 002e.4
constrain_resources: PNP: 002e.5
constrain_resources: PNP: 002e.7
constrain_resources: PNP: 002e.a
skipping PNP: 002...@60 fixed resource, size=0!
constrain_resources: PCI: 00:1f.1
constrain_resources: PCI: 00:1f.3
constrain_resources: PCI: 00:1f.5
avoid_fixed_resources2: PCI_DOMAIN: 0...@10000000 limit 0000ffff
lim->base 00001000 lim->limit 0000ffff
avoid_fixed_resources2: PCI_DOMAIN: 0...@10000100 limit ffffffff
lim->base 00000000 lim->limit febfffff
Setting resources...
PCI_DOMAIN: 0000 allocate_resources_io: base:1000 size:10a8 align:12 gran:0
limit:ffff
Assigned: PCI: 00:1e.0 1c * [0x1000 - 0x1fff] io
Assigned: PCI: 00:1d.0 20 * [0x2000 - 0x201f] io
Assigned: PCI: 00:1d.1 20 * [0x2020 - 0x203f] io
Assigned: PCI: 00:1d.2 20 * [0x2040 - 0x205f] io
Assigned: PCI: 00:1f.3 20 * [0x2060 - 0x207f] io
Assigned: PCI: 00:1f.1 20 * [0x2080 - 0x208f] io
Assigned: PCI: 00:1f.1 10 * [0x2090 - 0x2097] io
Assigned: PCI: 00:1f.1 18 * [0x2098 - 0x209f] io
Assigned: PCI: 00:1f.1 14 * [0x20a0 - 0x20a3] io
Assigned: PCI: 00:1f.1 1c * [0x20a4 - 0x20a7] io
PCI_DOMAIN: 0000 allocate_resources_io: next_base: 20a8 size: 10a8 align: 12
gran: 0 done
PCI: 00:1e.0 allocate_resources_io: base:1000 size:1000 align:12 gran:12
limit:ffff
Assigned: PCI: 01:08.0 14 * [0x1000 - 0x103f] io
PCI: 00:1e.0 allocate_resources_io: next_base: 1040 size: 1000 align: 12 gran:
12 done
PCI_DOMAIN: 0000 allocate_resources_mem: base:f8000000 size:4180b00 align:26
gran:0 limit:febfffff
Assigned: PCI: 00:02.0 10 * [0xf8000000 - 0xfbffffff] prefmem
Assigned: PCI: 00:1e.0 20 * [0xfc000000 - 0xfc0fffff] mem
Assigned: PCI: 00:02.0 14 * [0xfc100000 - 0xfc17ffff] mem
Assigned: PCI: 00:1d.7 10 * [0xfc180000 - 0xfc1803ff] mem
Assigned: PCI: 00:1f.1 24 * [0xfc180400 - 0xfc1807ff] mem
Assigned: PCI: 00:1f.5 18 * [0xfc180800 - 0xfc1809ff] mem
Assigned: PCI: 00:1f.5 1c * [0xfc180a00 - 0xfc180aff] mem
PCI_DOMAIN: 0000 allocate_resources_mem: next_base: fc180b00 size: 4180b00
align: 26 gran: 0 done
PCI: 00:1e.0 allocate_resources_prefmem: base:febfffff size:0 align:20 gran:20
limit:febfffff
PCI: 00:1e.0 allocate_resources_prefmem: next_base: febfffff size: 0 align: 20
gran: 20 done
PCI: 00:1e.0 allocate_resources_mem: base:fc000000 size:100000 align:20 gran:20
limit:febfffff
Assigned: PCI: 01:08.0 10 * [0xfc000000 - 0xfc000fff] mem
PCI: 00:1e.0 allocate_resources_mem: next_base: fc001000 size: 100000 align: 20
gran: 20 done
Root Device assign_resources, bus 0 link: 0
8MB IGD UMA
Available memory: 581632KB
PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0
PCI: 00:02.0 10 <- [0x00f8000000 - 0x00fbffffff] size 0x04000000 gran 0x1a
prefmem
PCI: 00:02.0 14 <- [0x00fc100000 - 0x00fc17ffff] size 0x00080000 gran 0x13 mem
PCI: 00:1d.0 20 <- [0x0000002000 - 0x000000201f] size 0x00000020 gran 0x05 io
PCI: 00:1d.1 20 <- [0x0000002020 - 0x000000203f] size 0x00000020 gran 0x05 io
PCI: 00:1d.2 20 <- [0x0000002040 - 0x000000205f] size 0x00000020 gran 0x05 io
PCI: 00:1d.7 10 <- [0x00fc180000 - 0x00fc1803ff] size 0x00000400 gran 0x0a mem
PCI: 00:1e.0 1c <- [0x0000001000 - 0x0000001fff] size 0x00001000 gran 0x0c bus
01 io
PCI: 00:1e.0 24 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus
01 prefmem
PCI: 00:1e.0 20 <- [0x00fc000000 - 0x00fc0fffff] size 0x00100000 gran 0x14 bus
01 mem
PCI: 00:1e.0 assign_resources, bus 1 link: 0
PCI: 01:08.0 10 <- [0x00fc000000 - 0x00fc000fff] size 0x00001000 gran 0x0c mem
PCI: 01:08.0 14 <- [0x0000001000 - 0x000000103f] size 0x00000040 gran 0x06 io
PCI: 00:1e.0 assign_resources, bus 1 link: 0
PCI: 00:1f.0 assign_resources, bus 0 link: 0
PNP: 002e.3 60 <- [0x0000000378 - 0x000000037f] size 0x00000008 gran 0x03 io
PNP: 002e.3 70 <- [0x0000000007 - 0x0000000007] size 0x00000001 gran 0x00 irq
PNP: 002e.3 74 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 drq
PNP: 002e.4 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io
PNP: 002e.4 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 irq
PNP: 002e.5 60 <- [0x00000002f8 - 0x00000002ff] size 0x00000008 gran 0x03 io
PNP: 002e.5 70 <- [0x0000000003 - 0x0000000003] size 0x00000001 gran 0x00 irq
PNP: 002e.7 60 <- [0x0000000060 - 0x0000000060] size 0x00000001 gran 0x00 io
PNP: 002e.7 62 <- [0x0000000064 - 0x0000000064] size 0x00000001 gran 0x00 io
PNP: 002e.7 70 <- [0x0000000001 - 0x0000000001] size 0x00000001 gran 0x00 irq
PNP: 002e.7 72 <- [0x000000000c - 0x000000000c] size 0x00000001 gran 0x00 irq
PNP: 002e.a 60 <- [0x0000000800 - 0x00000007ff] size 0x00000000 gran 0x00 io
PCI: 00:1f.0 assign_resources, bus 0 link: 0
PCI: 00:1f.1 10 <- [0x0000002090 - 0x0000002097] size 0x00000008 gran 0x03 io
PCI: 00:1f.1 14 <- [0x00000020a0 - 0x00000020a3] size 0x00000004 gran 0x02 io
PCI: 00:1f.1 18 <- [0x0000002098 - 0x000000209f] size 0x00000008 gran 0x03 io
PCI: 00:1f.1 1c <- [0x00000020a4 - 0x00000020a7] size 0x00000004 gran 0x02 io
PCI: 00:1f.1 20 <- [0x0000002080 - 0x000000208f] size 0x00000010 gran 0x04 io
PCI: 00:1f.1 24 <- [0x00fc180400 - 0x00fc1807ff] size 0x00000400 gran 0x0a mem
PCI: 00:1f.3 20 <- [0x0000002060 - 0x000000207f] size 0x00000020 gran 0x05 io
PCI: 00:1f.5 18 <- [0x00fc180800 - 0x00fc1809ff] size 0x00000200 gran 0x09 mem
PCI: 00:1f.5 1c <- [0x00fc180a00 - 0x00fc180aff] size 0x00000100 gran 0x08 mem
PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0
Root Device assign_resources, bus 0 link: 0
Done setting resources.
Show resources in subtree (Root Device)...After assigning values.
Root Device links 1 child on link 0 APIC_CLUSTER: 0
APIC_CLUSTER: 0 links 1 child on link 0 APIC: 00
APIC: 00 links 0 child on link 0 NULL
PCI_DOMAIN: 0000 links 1 child on link 0 PCI: 00:00.0
PCI_DOMAIN: 0000 resource base 1000 size 10a8 align 12 gran 0 limit ffff
flags 40040100 index 10000000
PCI_DOMAIN: 0000 resource base f8000000 size 4180b00 align 26 gran 0 limit
febfffff flags 40040200 index 10000100
PCI_DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags
e0004200 index a
PCI_DOMAIN: 0000 resource base 100000 size 23700000 align 0 gran 0 limit 0
flags e0004200 index b
PCI: 00:00.0 links 0 child on link 0 NULL
PCI: 00:02.0 links 0 child on link 0 NULL
PCI: 00:02.0 resource base f8000000 size 4000000 align 26 gran 26 limit
febfffff flags 60001200 index 10
PCI: 00:02.0 resource base fc100000 size 80000 align 19 gran 19 limit
febfffff flags 60000200 index 14
PCI: 00:1d.0 links 0 child on link 0 NULL
PCI: 00:1d.0 resource base 2000 size 20 align 5 gran 5 limit ffff flags
60000100 index 20
PCI: 00:1d.1 links 0 child on link 0 NULL
PCI: 00:1d.1 resource base 2020 size 20 align 5 gran 5 limit ffff flags
60000100 index 20
PCI: 00:1d.2 links 0 child on link 0 NULL
PCI: 00:1d.2 resource base 2040 size 20 align 5 gran 5 limit ffff flags
60000100 index 20
PCI: 00:1d.7 links 0 child on link 0 NULL
PCI: 00:1d.7 resource base fc180000 size 400 align 10 gran 10 limit febfffff
flags 60000200 index 10
PCI: 00:1e.0 links 1 child on link 0 PCI: 01:08.0
PCI: 00:1e.0 resource base 1000 size 1000 align 12 gran 12 limit ffff flags
60080102 index 1c
PCI: 00:1e.0 resource base febfffff size 0 align 20 gran 20 limit febfffff
flags 60081202 index 24
PCI: 00:1e.0 resource base fc000000 size 100000 align 20 gran 20 limit
febfffff flags 60080202 index 20
PCI: 01:08.0 links 0 child on link 0 NULL
PCI: 01:08.0 resource base fc000000 size 1000 align 12 gran 12 limit
febfffff flags 60000200 index 10
PCI: 01:08.0 resource base 1000 size 40 align 6 gran 6 limit ffff flags
60000100 index 14
PCI: 00:1f.0 links 1 child on link 0 PNP: 002e.0
PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100
index 10000000
PCI: 00:1f.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags
c0040200 index 10000100
PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags
c0000200 index 3
PNP: 002e.0 links 0 child on link 0 NULL
PNP: 002e.0 resource base 3f0 size 8 align 3 gran 3 limit 7ff flags
c0000100 index 60
PNP: 002e.0 resource base 6 size 1 align 0 gran 0 limit 0 flags c0000400
index 70
PNP: 002e.0 resource base 2 size 1 align 0 gran 0 limit 0 flags c0000800
index 74
PNP: 002e.3 links 0 child on link 0 NULL
PNP: 002e.3 resource base 378 size 8 align 3 gran 3 limit 7ff flags
e0000100 index 60
PNP: 002e.3 resource base 7 size 1 align 0 gran 0 limit 0 flags e0000400
index 70
PNP: 002e.3 resource base 4 size 1 align 0 gran 0 limit 0 flags e0000800
index 74
PNP: 002e.4 links 0 child on link 0 NULL
PNP: 002e.4 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags
e0000100 index 60
PNP: 002e.4 resource base 4 size 1 align 0 gran 0 limit 0 flags e0000400
index 70
PNP: 002e.5 links 0 child on link 0 NULL
PNP: 002e.5 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags
e0000100 index 60
PNP: 002e.5 resource base 3 size 1 align 0 gran 0 limit 0 flags e0000400
index 70
PNP: 002e.7 links 0 child on link 0 NULL
PNP: 002e.7 resource base 60 size 1 align 0 gran 0 limit ffffffff flags
e0000100 index 60
PNP: 002e.7 resource base 64 size 1 align 0 gran 0 limit ffffffff flags
e0000100 index 62
PNP: 002e.7 resource base 1 size 1 align 0 gran 0 limit 0 flags e0000400
index 70
PNP: 002e.7 resource base c size 1 align 0 gran 0 limit 0 flags e0000400
index 72
PNP: 002e.9 links 0 child on link 0 NULL
PNP: 002e.a links 0 child on link 0 NULL
PNP: 002e.a resource base 800 size 0 align 0 gran 0 limit 0 flags e0000100
index 60
PNP: 002e.b links 0 child on link 0 NULL
PCI: 00:1f.1 links 0 child on link 0 NULL
PCI: 00:1f.1 resource base 2090 size 8 align 3 gran 3 limit ffff flags
60000100 index 10
PCI: 00:1f.1 resource base 20a0 size 4 align 2 gran 2 limit ffff flags
60000100 index 14
PCI: 00:1f.1 resource base 2098 size 8 align 3 gran 3 limit ffff flags
60000100 index 18
PCI: 00:1f.1 resource base 20a4 size 4 align 2 gran 2 limit ffff flags
60000100 index 1c
PCI: 00:1f.1 resource base 2080 size 10 align 4 gran 4 limit ffff flags
60000100 index 20
PCI: 00:1f.1 resource base fc180400 size 400 align 10 gran 10 limit febfffff
flags 60000200 index 24
PCI: 00:1f.3 links 0 child on link 0 NULL
PCI: 00:1f.3 resource base 2060 size 20 align 5 gran 5 limit ffff flags
60000100 index 20
PCI: 00:1f.5 links 0 child on link 0 NULL
PCI: 00:1f.5 resource base fc180800 size 200 align 9 gran 9 limit febfffff
flags 60000200 index 18
PCI: 00:1f.5 resource base fc180a00 size 100 align 8 gran 8 limit febfffff
flags 60000200 index 1c
PCI: 00:1f.6 links 0 child on link 0 NULL
Done allocating resources.
Enabling resources...
PCI: 00:00.0 cmd <- 06
PCI: 00:02.0 cmd <- 03
PCI: 00:1d.0 cmd <- 01
PCI: 00:1d.1 cmd <- 01
PCI: 00:1d.2 cmd <- 01
PCI: 00:1d.7 cmd <- 02
PCI: 00:1e.0 bridge ctrl <- 0003
PCI: 00:1e.0 cmd <- 07
PCI: 01:08.0 cmd <- 03
PCI: 00:1f.0 cmd <- 0f
PCI: 00:1f.1 cmd <- 03
PCI: 00:1f.3 subsystem <- 00/00
PCI: 00:1f.3 cmd <- 01
PCI: 00:1f.5 cmd <- 02
done.
Initializing devices...
Root Device init
APIC_CLUSTER: 0 init
Initializing SMM handler... ... pmbase = 0x0400
SMI_STS: PM1
PM1_STS: TMROF
GPE0_STS:
ALT_GP_SMI_STS:
TCO_STS:
... raise SMI#
Initializing CPU #0
CPU: vendor Intel device 6b4
CPU: family 06, model 0b, stepping 04
Enabling cache
Setting fixed MTRRs(0-88) Type: UC
Setting fixed MTRRs(0-16) Type: WB
DONE fixed MTRRs
call enable_fixed_mtrr()
Setting variable MTRR 0, base: 0MB, range: 512MB, type WB
ADDRESS_MASK_HIGH=0xf
Setting variable MTRR 1, base: 512MB, range: 64MB, type WB
ADDRESS_MASK_HIGH=0xf
Setting variable MTRR 2, base: 568MB, range: 8MB, type UC
ADDRESS_MASK_HIGH=0xf
DONE variable MTRRs
Clear out the extra MTRR's
call enable_var_mtrr()
Leave x86_setup_var_mtrrs
MTRR check
Fixed MTRRs : Enabled
Variable MTRRs: Enabled
microcode_info: sig = 0x000006b4 pf=0x00000010 rev = 0x00000000
Setting up local apic... apic_id: 0x00 done.
CPU #0 initialized
PCI: 00:00.0 init
Northbridge init
PCI: 00:02.0 init
Starting Graphics Initialization
Check CBFS header at fffeffe0
magic is 4f524243
Found CBFS header at fffeffe0
Check fallback/coreboot_ram
CBFS: follow chain: fff80000 + 38 + 96ab + align -> fff89700
Check pci8086,3577.rom
CBFS: follow chain: fff89700 + 38 + 10000 + align -> fff99740
Check
CBFS: follow chain: fff99740 + 28 + 56878 + align -> ffff0000
Could not find MBI.
Check CBFS header at fffeffe0
magic is 4f524243
Found CBFS header at fffeffe0
Check fallback/coreboot_ram
CBFS: follow chain: fff80000 + 38 + 96ab + align -> fff89700
Check pci8086,3577.rom
In cbfs, rom address for PCI: 00:02.0 = fff89738
PCI Expansion ROM, signature 0xaa55, INIT size 0x10000, data ptr 0x0040
PCI ROM Image, Vendor 8086, Device 3577,
PCI ROM Image, Class Code 030000, Code Type 00
copying VGA ROM Image from fff89738 to 0xc0000, 0x10000 bytes
Real mode stub @00000600: 422 bytes
Calling Option ROM...
... Option ROM returned.
Graphics Initialization Complete
PCI: 00:1d.0 init
USB: Setting up controller.. done.
PCI: 00:1d.1 init
USB: Setting up controller.. done.
PCI: 00:1d.2 init
USB: Setting up controller.. done.
PCI: 00:1d.7 init
USB: Setting up controller.. done.
PCI: 00:1f.0 init
IOAPIC Southbridge enabled 2186
Southbridge APIC ID = 2000000
Set power on if power fails
RTC Init
PNP: 002e.3 init
PNP: 002e.4 init
PNP: 002e.5 init
PNP: 002e.7 init
Keyboard init...
Keyboard controller output buffer result timeout
PNP: 002e.a init
PCI: 00:1f.1 init
IDE0: Primary IDE interface is enabled
IDE1: Secondary IDE interface is enabled
PCI: 00:1f.3 init
Check CBFS header at fffeffe0
magic is 4f524243
Found CBFS header at fffeffe0
Check fallback/coreboot_ram
CBFS: follow chain: fff80000 + 38 + 96ab + align -> fff89700
Check pci8086,3577.rom
CBFS: follow chain: fff89700 + 38 + 10000 + align -> fff99740
Check
CBFS: follow chain: fff99740 + 28 + 56878 + align -> ffff0000
CBFS: Could not find file pci8086,24c3.rom
PCI: 00:1f.5 init
Initializing AC'97 Audio.
No primary codec. Disabling AC'97 Audio.
PCI: 01:08.0 init
Check CBFS header at fffeffe0
magic is 4f524243
Found CBFS header at fffeffe0
Check fallback/coreboot_ram
CBFS: follow chain: fff80000 + 38 + 96ab + align -> fff89700
Check pci8086,3577.rom
CBFS: follow chain: fff89700 + 38 + 10000 + align -> fff99740
Check
CBFS: follow chain: fff99740 + 28 + 56878 + align -> ffff0000
CBFS: Could not find file pci8086,103a.rom
Devices initialized
Show all devs...After init.
Root Device: enabled 1, 0 resources
APIC_CLUSTER: 0: enabled 1, 0 resources
APIC: 00: enabled 1, 0 resources
PCI_DOMAIN: 0000: enabled 1, 4 resources
PCI: 00:00.0: enabled 1, 0 resources
PCI: 00:02.0: enabled 1, 2 resources
PCI: 00:1d.0: enabled 1, 1 resources
PCI: 00:1d.1: enabled 1, 1 resources
PCI: 00:1d.2: enabled 1, 1 resources
PCI: 00:1d.7: enabled 1, 1 resources
PCI: 00:1e.0: enabled 1, 3 resources
PCI: 00:1f.0: enabled 1, 3 resources
PNP: 002e.0: enabled 0, 3 resources
PNP: 002e.3: enabled 1, 3 resources
PNP: 002e.4: enabled 1, 2 resources
PNP: 002e.5: enabled 1, 2 resources
PNP: 002e.7: enabled 1, 4 resources
PNP: 002e.9: enabled 0, 0 resources
PNP: 002e.a: enabled 1, 1 resources
PNP: 002e.b: enabled 0, 0 resources
PCI: 00:1f.1: enabled 1, 6 resources
PCI: 00:1f.3: enabled 1, 1 resources
PCI: 00:1f.5: enabled 1, 2 resources
PCI: 00:1f.6: enabled 0, 0 resources
PCI: 01:08.0: enabled 1, 2 resources
Initializing CBMEM area to 0x237f0000 (65536 bytes)
Adding CBMEM entry as no. 1
Moving GDT to 237f0200...ok
High Tables Base is 237f0000.
Copying Interrupt Routing Table to 0x000f0000... done.
Adding CBMEM entry as no. 2
Copying Interrupt Routing Table to 0x237f0400... done.
PIRQ table: 144 bytes.
Multiboot Information structure has been written.
Adding CBMEM entry as no. 3
Writing high table forward entry at 0x00000500
Wrote coreboot table at: 00000500 - 00000518 checksum c85f
New low_table_end: 0x00000518
Now going to write high coreboot table at 0x237f1400
rom_table_end = 0x237f1400
Adjust low_table_end from 0x00000518 to 0x00001000
Adjust rom_table_end from 0x237f1400 to 0x23800000
Adding high table area
Adding IGD UMA memory area
coreboot memory table:
0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
1. 0000000000001000-000000000009ffff: RAM
2. 0000000000100000-00000000237effff: RAM
3. 00000000237f0000-00000000237fffff: CONFIGURATION TABLES
4. 0000000023800000-0000000023ffffff: RESERVED
Wrote coreboot table at: 237f1400 - 237f1594 checksum 6cf7
coreboot table: 404 bytes.
0. FREE SPACE 237f3400 0000cc00
1. GDT 237f0200 00000200
2. IRQ TABLE 237f0400 00001000
3. COREBOOT 237f1400 00002000
Check CBFS header at fffeffe0
magic is 4f524243
Found CBFS header at fffeffe0
Check fallback/coreboot_ram
CBFS: follow chain: fff80000 + 38 + 96ab + align -> fff89700
Check pci8086,3577.rom
CBFS: follow chain: fff89700 + 38 + 10000 + align -> fff99740
Check
CBFS: follow chain: fff99740 + 28 + 56878 + align -> ffff0000
CBFS: Could not find file fallback/payload
Boot failed.
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