Index: i82371eb.h
===================================================================
--- i82371eb.h	(revision 5309)
+++ i82371eb.h	(working copy)
@@ -55,6 +55,22 @@
 #define PMBA		0x40	/* Power management base address */
 #define PMREGMISC	0x80	/* Miscellaneous power management */
 
+/* Device resources */
+#define DEVRESA		0x5c	/* Device Resource A */
+#define DEVRESB		0x60	/* Device Resource B */
+#define DEVRESC		0x64	/* Device Resource C */
+#define DEVRESD		0x50	/* Device Resource D */
+#define DEVRESE		0x68	/* Device Resource E */
+#define DEVRESF		0x6c	/* Device Resource F */
+#define DEVRESG		0x70	/* Device Resource G */
+#define DEVRESH		0x74	/* Device Resource H */
+#define DEVRESI		0x78	/* Device Resource I */
+#define DEVRESJ		0x7c	/* Device Resource J */
+
+/* Device activity */
+#define DEVACTA		0x54	/* Device Activity A */
+#define DEVACTB		0x58	/* Device Activity B */
+
 /* Bit definitions */
 #define EXT_BIOS_ENABLE_1MB	(1 << 9)  /* 1-Meg Extended BIOS Enable */
 #define EXT_BIOS_ENABLE		(1 << 7)  /* Extended BIOS Enable */
@@ -73,4 +89,7 @@
 #define ISA			(1 << 0)  /* Select ISA */
 #define EIO			(0 << 0)  /* Select EIO */
 
+/* Power Management Base Address */
+#define PM_IO_BASE 0xe400
+
 #endif /* SOUTHBRIDGE_INTEL_I82371EB_I82371EB_H */
Index: i82371eb_smbus.c
===================================================================
--- i82371eb_smbus.c	(revision 5309)
+++ i82371eb_smbus.c	(working copy)
@@ -2,6 +2,7 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
+ * Copyright (C) 2010 Keith Hui <buurin@gmail.com>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -25,7 +26,57 @@
 #include <device/smbus.h>
 #include "i82371eb.h"
 
-/* TODO: Needed later? */
+/* Table format: register, bitmask, value. */
+static const u8 register_values[] = {
+	/* DEVRESE — Device Resource E
+	 * 0x68 - 0x6A
+	 *
+	 * [23:21] Reserved
+	 * [20:20] Device 12 I/O Monitor Enable (IO_EN_DEV12)
+	 *         0 = Enable PCI bus decode for accesses to the I/O address 
+	 *             range selected by the IBASE_DEV12 and IMASK_DEV12 fields
+	 *         1 = Disable
+	 * [19:16] Device 12 I/O Decode Mask (IMASK_DEV12)
+	 *         Specifies the 4-bit I/O base address mask used to determine 
+	 *         the IO address range size for device 12 accesses. 
+	 *         IMASK_DEV12 (bits[19:16]) correspond to AD[3:0]. A '1' in a 
+	 *         bit position indicates that the corresponding address bit is 
+	 *         masked (i.e. ignored) when performing the decode. Note that 
+	 *         programming these bits to certain patterns (such as '1001') 
+	 *         results in a split address range.
+	 * [15:00] Device 12 I/O Decode Base Address (IBASE_DEV12)
+	 *         Specifies the 16-bit I/O base address range (AD[15:0]) for the 
+	 *         device 12 I/O range. When this field is combined with IMASK_DEV12 
+	 *         field, an I/O range is defined starting from the base address 
+	 *         register value to the size defined by the mask register.
+	 */
+	// Set device 12 I/O range at 0xe404-0xe405 and enable.
+	DEVRESE + 0, 0x00, 0x04,
+	DEVRESE + 1, 0x00, 0xe4,
+	DEVRESE + 2, 0x00, 0x11,
+};
+
+static void pwrmgt_init(struct device *dev)
+{
+	int i, max;
+	u8 reg;
+
+	/* Sets the base address of power management ports. */
+	pci_write_config16(dev, PMBA, PM_IO_BASE | 1);
+	
+	/* Initialize other aspects of PIIX4 power management,
+	 * using the same approach in i440bx/raminit.c. */
+	max = sizeof(register_values);
+
+	/* Set registers as specified in the register_values[] array. */
+	for (i = 0; i < max; i += 3) {
+		reg = pci_read_config8(dev, register_values[i]);
+		reg &= register_values[i + 1];
+		reg |= register_values[i + 2];
+		pci_write_config8(dev, register_values[i], reg);
+	}
+}
+
 static const struct smbus_bus_operations lops_smbus_bus = {
 };
 
@@ -33,7 +84,7 @@
 	.read_resources		= pci_dev_read_resources,
 	.set_resources		= pci_dev_set_resources,
 	.enable_resources	= pci_dev_enable_resources,
-	.init			= 0,
+	.init			= pwrmgt_init,
 	.scan_bus		= scan_static_bus,
 	.enable			= 0,
 	.ops_pci		= 0, /* No subsystem IDs on 82371EB! */